Stacked Semiconductor Package Layout for Heat and Warpage Control
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved thermal characteristics, electrical characteristics, and warpage resistance, which are crucial for reliability and miniaturization.
Innovation Solution
A semiconductor package design incorporating a conductive layer in direct contact with the upper semiconductor chip, connected to lower conductive structures, and a redistribution substrate with specific insulation and conductive patterns, enhancing thermal dissipation and electrical connectivity while reducing warpage through differential thermal expansion coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If semiconductor chips are mounted on a printed circuit board using bonding wires or bumps, then electrical connectivity is achieved, but thermal dissipation is insufficient and warpage occurs
Solution Approach 1:
The patent introduces a conductive layer with specific thermal and electrical conductivity parameters directly contacting the upper semiconductor chip. This layer has higher thermal conductivity than conventional bonding wires, enabling improved heat dissipation while maintaining electrical connectivity. The conductive layer's physical and chemical properties are optimized to match the semiconductor chip characteristics, resolving the thermal management issue without causing warpage.
Solution Approach 2:
The patent employs a composite structure consisting of the upper semiconductor chip, the conductive layer, and the lower conductive structure. This composite design integrates multiple materials with complementary properties: the semiconductor chip for electronic function, the conductive layer for superior thermal and electrical conductivity, and the lower conductive structure for mechanical support and additional conductivity. This composite approach simultaneously achieves excellent thermal dissipation and warpage resistance.
2Reliability
If conventional bonding wires or bumps are used for electrical connection, then electrical connectivity is established, but electrical characteristics and reliability are limited
Solution Approach 1:
The patent extracts and eliminates the conventional bonding wire or bump connection method between the upper semiconductor chip and the lower conductive structure. By removing this intermediate connection element, the invention directly contacts the upper semiconductor chip with the conductive layer, simplifying the connection structure while improving electrical characteristics through direct contact and reduced resistance.
Solution Approach 2:
The patent merges the thermal management function and electrical connectivity function into a single integrated conductive layer. This layer simultaneously serves as both a heat dissipation pathway and an electrical connection medium, eliminating the need for separate bonding wires or bumps. This merging approach reduces device complexity while enhancing electrical reliability and thermal performance.
3Volume of moving object
If miniaturization is pursued in semiconductor packages, then compactness is achieved, but thermal management and warpage control become more difficult
Solution Approach 1:
The patent introduces the conductive layer as an intermediary element between the upper semiconductor chip and the lower conductive structure. This intermediary layer provides an efficient thermal conduction pathway that bridges the gap in miniaturized packages, enabling effective heat dissipation from the chip to the external environment despite the reduced overall package size. The conductive layer's high thermal conductivity compensates for the shorter thermal pathways available in compact designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves thermal dissipation, reduces warpage, and enhances electrical reliability by stabilizing voltage supply and shielding against electromagnetic interference, allowing for more compact and reliable semiconductor packages.
Implementation Method 1
a conductive layer in direct contact with a top surface of the upper semiconductor chip
Implementation Method 2
reducing warpage through differential thermal expansion coefficients
Implementation Method 3
electrically connected to the first lower conductive structure
Data Source
AI summary
A semiconductor package includes: a first substrate; a lower semiconductor chip on the first substrate and including a through via; an upper semiconductor chip on the lower semiconductor chip and connected to the through via; a first lower conductive structure on the first substrate and laterally spaced apart from the lower semiconductor chip; a second lower conductive structure on the first substrate and laterally spaced apart from the lower semiconductor chip and the first lower conductive structure; an upper conductive structure on the second lower conductive structure; a conductive layer in direct physical contact with a top surface of the upper semiconductor chip and electrically connected to the first lower conductive structure; and a second substrate on the conductive layer and electrically connected to the upper conductive structure.