Stacked Semiconductor Package Without TSVs for High I/O Density
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Solution Overview
Problem
Existing semiconductor packages face challenges in ensuring reliable connection and integration of highly integrated semiconductor chips with a large number of input/output (I/O) connection terminals, particularly in miniaturized and high-capacity devices.
Innovation Solution
A semiconductor package design featuring a stacked structure of semiconductor chips with double-sided configurations, utilizing both conductive posts and wires for electrical connections, and a redistribution structure on a package substrate to enhance connectivity and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of I/O connection terminals are used to achieve high integration, then the functionality and capacity of semiconductor devices increase, but the package size and connection complexity increase
Solution Approach 1:
The patent transitions from a planar arrangement of I/O terminals to a three-dimensional stacked configuration of semiconductor chips. Multiple chips are vertically stacked with interconnections formed between layers, enabling high I/O capacity without increasing the lateral package footprint. This vertical integration allows numerous connection terminals to be accommodated within a compact volume by utilizing the third dimension.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked one on top of another, with each chip containing functional devices and interconnection structures. The chips are nested vertically with lower chips supporting upper chips, and interconnection structures penetrate through multiple layers to establish electrical connections. This nesting approach maximizes the number of I/O terminals within a minimal package area.
2Speed
If through silicon vias (TSVs) are used to achieve vertical interconnections in stacked chips, then signal transfer speed improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the interconnection structure into segmented components rather than using continuous through silicon vias. The interconnection is achieved through a combination of conductive posts on chip surfaces, wire bonds connecting adjacent chips, and redistribution layers. This segmentation simplifies manufacturing by allowing each component to be formed using separate, well-established processes rather than requiring complex TSV formation through entire chip thicknesses.
Solution Approach 2:
The patent introduces wire bonds as intermediary elements between conductive posts on lower chips and corresponding contact structures on upper chips. These wire bonds serve as mediators that establish vertical electrical connections without requiring direct through-silicon penetration. The wire bonds bridge the gap between layers, enabling signal transmission while avoiding the manufacturing complexity of TSVs.
Data Source
AI summary
A semiconductor package includes: a package substrate and a plurality of semiconductor chips stacked on the package substrate in a vertical direction, wherein each of the plurality of semiconductor chips includes a semiconductor substrate including a first surface, a lower semiconductor device on the first surface, a second surface opposite to the first surface, and an upper semiconductor device on the second surface, a lower wiring structure disposed on the first surface, and an upper wiring structure disposed on the second surface.