Stacked Electronic Package Layout for High-I/O Thin Substrates
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Solution Overview
Problem
The increasing number of input/output connections in semiconductor chips leads to thicker semiconductor substrates, which in turn decreases yield due to increased circuit layers, posing challenges in manufacturing and performance.
Innovation Solution
The electronic package incorporates a first and second circuit pattern structure with a gap between them, where the second circuit pattern structure has a higher density of circuit lines and is positioned over the first, with an encapsulant filling the gap and connecting the structures, reducing thickness and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of I/O connections is increased, then the electrical performance and functions are improved, but the thickness of the semiconductor substrate increases and yield decreases
Solution Approach 1:
The patent transitions from a planar circuit layout to a three-dimensional stacked architecture with multiple circuit layers (first circuit pattern structure, second circuit pattern structure) connected via vertical conductive structures. This vertical stacking enables increased I/O connections without proportionally increasing substrate thickness, as connections are distributed across multiple layers rather than confined to a single plane.
Solution Approach 2:
The patent implements nested circuit patterns where the second circuit pattern structure is positioned over the first circuit pattern structure, with conductive structures extending vertically between layers. This nesting approach allows circuit elements to be arranged in multiple dimensions, increasing connection density while maintaining a compact overall thickness.
2Adaptability or versatility
If the number of circuit layers is increased, then the number of I/O connections is improved, but the thickness of the semiconductor substrate increases and yield decreases
Solution Approach 1:
The patent divides the circuit interconnection system into segmented layers (first circuit pattern structure, second circuit pattern structure) separated by an encapsulant. This segmentation allows each layer to be independently optimized and manufactured, potentially improving yield by isolating defects to specific layers rather than compromising the entire substrate.
Solution Approach 2:
The encapsulant serves as an intermediary material between the first and second circuit pattern structures. It provides mechanical support, electrical isolation, and structural stability, enabling the multi-layer configuration to function reliably while maintaining manufacturing yield through improved defect isolation and structural integrity.
3Adaptability or versatility
If the circuit layers are increased to achieve more I/O connections, then the functionality is improved, but the thickness increases leading to warpage and reduced attachment
Solution Approach 1:
The patent employs composite material structures combining different circuit pattern layers, conductive materials, and encapsulant materials. This composite approach allows optimization of each material's properties for its specific function while maintaining overall structural stability and reducing warpage through balanced material selection and layer configuration.
Solution Approach 2:
The encapsulant acts as a mediator between the circuit pattern structures, providing mechanical coupling and stress distribution. This intermediary layer enhances attachment between layers and reduces warpage by distributing thermal and mechanical stresses uniformly across the multi-layer structure.
Data Source
AI summary
An electronic package includes an electronic structure, a first circuit pattern structure, a plurality of first solders and an encapsulant. The electronic structure includes an electronic device, and has a top surface and a bottom surface opposite to the top surface. The first circuit pattern structure is disposed over the top surface of the electronic structure. The first solders are disposed on the bottom surface of the electronic structure. The encapsulant encapsulates the electronic structure. At least a portion of the encapsulant is disposed between at least two of the plurality of first solders.