Stepped Stacked Semiconductor Package for Higher Integration
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Solution Overview
Problem
Conventional semiconductor packages face challenges in reducing the overall size and increasing the integration of semiconductor chips while maintaining reliable electrical connections and preventing damage to memory cells during high-temperature processing.
Innovation Solution
The solution involves stacking semiconductor structures with a smaller peripheral circuit chip on top of a larger memory chip, forming a stepped structure, and using adhesive layers with specific thickness and positioning to facilitate efficient bonding and reduce the horizontal size of the package, while preventing memory cell damage through separate fabrication of sub-chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase integration, then the integration level increases, but the horizontal size of the package increases
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking, arranging semiconductor chips in the thickness direction (z-axis) rather than spreading them horizontally. This dimensional change allows multiple chips to be integrated without increasing the package's horizontal footprint, directly resolving the contradiction between integration level and horizontal size.
Solution Approach 2:
The patent implements a nested structure where peripheral circuit chips are positioned on top of memory chips, with smaller chips nested within the horizontal footprint of larger chips below. This nesting approach maximizes vertical space utilization and maintains compact horizontal dimensions while achieving high integration.
2Reliability
If adhesive layers are used to bond semiconductor chips, then reliable electrical connections are achieved, but the complexity of the bonding process increases
Solution Approach 1:
The patent applies adhesive layers selectively only in specific regions where memory chips are bonded to peripheral circuit chips, rather than uniformly across all chip surfaces. This localized application maintains reliable electrical connections at critical interfaces while reducing overall bonding complexity and material usage.
Solution Approach 2:
The bonding process is segmented into distinct stages: first bonding memory chips to the substrate, then bonding peripheral circuit chips to the memory chips. This segmentation simplifies the overall bonding process by breaking it into manageable steps, each with specific adhesive application requirements, reducing overall process complexity while maintaining connection reliability.
3Ease of manufacture
If high-temperature processing is used during manufacturing, then proper bonding and curing are achieved, but memory cell damage occurs
Solution Approach 1:
The patent performs preliminary bonding of memory chips to peripheral circuit chips using adhesive layers before subjecting the assembly to high-temperature processing. This preliminary action ensures that chips are securely positioned and protected, allowing high-temperature curing to proceed without causing memory cell damage from improper positioning or exposure.
Solution Approach 2:
The adhesive layers serve as a cushioning medium that protects memory cells during high-temperature processing. By applying these adhesive layers beforehand, the patent creates a protective barrier that absorbs thermal stress and prevents direct damage to memory cells, enabling effective bonding and curing without compromising cell integrity.
4Area of stationary object
If the package size is reduced, then integration density increases, but the risk of damage during assembly increases
Solution Approach 1:
The patent reduces package horizontal size by utilizing the vertical dimension for chip stacking. This dimensional transition allows compact packaging without compromising assembly reliability, as the vertical arrangement provides stable mechanical support and clear separation between chips, reducing assembly risks despite reduced horizontal footprint.
Data Source
AI summary
A semiconductor package includes a plurality of first semiconductor structures that are stacked on a package substrate and are offset from each other in a first direction, and a plurality of first adhesive layers disposed between the first semiconductor structures. Each of the first semiconductor structures includes a first sub-chip and a second sub-chip in contact with a part of a top surface of the first sub-chip. The first adhesive layers are disposed between and are in contact with the first sub-chips. The first adhesive layers are spaced apart from the second sub-chips. A thickness of each of the first adhesive layers is less than a thickness of each of the second sub-chips. The thickness of the second sub-chip is in a range of about 13 μm to about 20 μm.