Stacked Semiconductor Package With Hybrid-Bonded Passive Component

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Solution Overview

Problem

In semiconductor package technology, passive components like capacitors have long electrical connection paths with semiconductor chips, limiting performance improvement and preventing fine pitch connections to main boards or package boards.

Innovation Solution

The semiconductor package includes a passive component with a short electrical connection path to a semiconductor chip, achieved through hybrid bonding on the first semiconductor chip, allowing for fine pitch connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a passive component is mounted side by side with the lower semiconductor chip on a package board or mounted along with solder balls on a lower surface of a main board, then the passive component can be electrically connected to the semiconductor chip, but the electrical connection path becomes long and fine pitch connection is not achieved

Engineering Contradiction:
Improveelectrical connection performanceVSAvoidelectrical connection path length
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent transitions from planar mounting (side by side on package board) to vertical stacking (passive component on lower semiconductor chip). This dimensional change shortens the electrical connection path by eliminating intermediate connection layers and enabling direct bonding between pads on adjacent surfaces, resolving the contradiction between achieving electrical connection and maintaining short path length.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a passive component is mounted side by side with the lower semiconductor chip on a package board, then the passive component can be electrically connected to the semiconductor chip, but fine pitch connection cannot be implemented

Engineering Contradiction:
Improveelectrical connection performanceVSAvoidconnection pitch
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

By moving from 2D planar arrangement to 3D vertical stacking, the patent enables finer pitch connections. The direct bonding interface between the lower semiconductor chip and passive component allows for smaller pad dimensions and tighter spacing, achieving fine pitch connection that is not possible with traditional side-by-side mounting.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Length of moving object

If hybrid bonding is used to position the passive component on the first semiconductor chip, then the electrical connection path is shortened and fine pitch connection is enabled, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveelectrical connection path lengthVSAvoidmanufacturing process complexity
Core Design Contradiction:
Length of moving objectVSEase of manufacture

Solution Approach 1:

The patent combines multiple functions into the hybrid bonding process: mechanical attachment, electrical connection, and positioning are all achieved simultaneously through direct pad-to-pad bonding. This merging of functions, while technically complex, eliminates the need for separate mounting and connection steps, ultimately simplifying the overall manufacturing workflow despite the advanced bonding requirements.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the performance of semiconductor chips by reducing electrical connection path length and enabling fine pitch connections, thereby improving overall package performance.

Implementation Method 1

The positioning of the passive component on the first semiconductor is performed by hybrid bonding

Methodology Applied
Scientific EffectHybrid bonding: Diffusion Welding

Data Source

PatentUS20250062260A1Semiconductor package and manufacturing method for the same
Publication Date: 2025.02.20 SAMSUNG ELECTRONICS CO LTD
  • US20250062260A1 patent drawing
  • US20250062260A1 patent drawing
  • US20250062260A1 patent drawing

AI summary

A semiconductor package includes: a substrate; a first semiconductor chip disposed on the substrate; a second semiconductor chip disposed on the first semiconductor chip; a passive component disposed on the first semiconductor chip; and an encapsulant that encapsulates the second semiconductor chip and the passive component. The first semiconductor chip includes a first through via that extends through at least a portion of the first semiconductor chip, and a first pad disposed on a first surface thereof and connected to the first through via. The passive component includes at least one trench and a second pad disposed on a first surface thereof and connected to the trench. The first pad and the second pad are directly bonded by contacting each other.