Stacked Semiconductor Package With Unified Insulating Film
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Solution Overview
Problem
Current semiconductor packages face challenges in efficiently and cost-effectively stacking semiconductor chips with through silicon vias (TSVs) in a vertical direction while maintaining reliability and functionality.
Innovation Solution
A semiconductor package design that uses a redistribution substrate with a single filling insulating film to cover multiple semiconductor chips, including dummy chips, allowing for efficient electrical connections and cost-effective fabrication by using a hybrid bonding method for chip integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate filling insulating films are used to cover each semiconductor chip individually, then each chip is properly insulated and protected, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent merges multiple separate filling insulating films into a single unified filling insulating film that covers all semiconductor chips (first, second, and third chips) simultaneously. This single film is formed in one continuous process step, eliminating the need for multiple separate deposition and patterning operations. The film is configured to fill spaces between chips and extend over their upper surfaces, providing comprehensive insulation and protection while simplifying the manufacturing process to a single application step.
2Reliability
If multiple separate filling insulating films are used to cover each semiconductor chip individually, then each chip is properly insulated and protected, but material costs and processing time increase
Solution Approach 1:
The patent combines multiple insulation operations into a single unified filling insulating film application. This single film is deposited in one continuous process, covering all semiconductor chips and inter-chip spaces simultaneously. This approach reduces material consumption by eliminating redundant film layers and interface structures, decreases processing time by performing one deposition operation instead of multiple sequential operations, and lowers overall fabrication costs while maintaining adequate insulation and protection for all chips.
3Device complexity
If a single filling insulating film is used to cover all semiconductor chips, then manufacturing cost and process complexity are reduced, but ensuring adequate insulation between chips becomes more challenging
Solution Approach 1:
The filling insulating film is configured with varying thickness and coverage in different regions to provide locally optimized insulation. The film fills the spaces between chips where insulation is most critical, and extends over the upper surfaces of chips with sufficient thickness to prevent electrical interference. This localized quality distribution ensures adequate insulation between adjacent chips while maintaining process simplicity, as the single film structure naturally provides different insulation levels where needed without requiring multiple patterned layers.
Data Source
AI summary
A semiconductor package includes a redistribution substrate. A first semiconductor chip is disposed on the redistribution substrate. The first semiconductor chip includes a first semiconductor substrate, first through vias penetrating through the first semiconductor substrate, and a first bonding layer disposed on the first semiconductor substrate. The first bonding layer is electrically connected to the first through vias. A second semiconductor chip includes a second semiconductor substrate and a second bonding layer disposed on the second semiconductor substrate. The second bonding layer is bonded to the first bonding layer. A filling insulating film is disposed on the redistribution substrate. The filling insulating film covers the first semiconductor chip and the second semiconductor chip. An upper surface of the filling insulating film is disposed on a level above an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip.