Stacked Semiconductor Package Interconnects for Heat and Stability

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving structural stability, thermal radiation efficiency, and operating stability, particularly in multi-chip stacked configurations, which are crucial for high-performance, compact electronic devices.

Innovation Solution

A semiconductor package design featuring a first die with a central region and peripheral region, through electrodes, and a dielectric layer, along with connection terminals that include convex portions to enhance structural stability and thermal radiation efficiency, while maintaining electrical stability through controlled pad widths and convex protrusions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multi-chip stacked package technique is used to achieve compact and high-performance products, then functionality and integration are improved, but structural stability and thermal radiation efficiency deteriorate

Engineering Contradiction:
ImprovefunctionalityVSAvoidstructural stability
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The connection terminals are designed with different geometries in different regions: convex portions protrude from the lateral surfaces of the connection terminals, creating local structural variations that enhance mechanical interlocking and structural stability in the multi-chip stacked package

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The convex portions on the connection terminals introduce curved geometric features that improve mechanical bonding between chips, enhancing structural stability through better stress distribution and interlocking

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Area of stationary object

If multi-chip stacked package technique is used to achieve compact products, then planar size is reduced, but thermal radiation efficiency deteriorates

Engineering Contradiction:
Improveplanar sizeVSAvoidthermal radiation efficiency
Core Design Contradiction:
Area of stationary objectVSLoss of energy

Solution Approach 1:

The connection terminals feature convex portions with specific geometries that increase the surface area for thermal radiation, improving heat dissipation efficiency despite the compact planar size of the multi-chip stacked package

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The convex portions extend in the lateral direction from the connection terminals, adding dimensional complexity that enhances thermal radiation surface area without increasing the planar footprint of the package

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Strength

If connection terminals are designed with convex portions to improve structural stability, then mechanical strength is improved, but device complexity increases

Engineering Contradiction:
Improvemechanical strengthVSAvoiddevice complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The convex portions are strategically positioned on the lateral surfaces of the connection terminals, providing localized mechanical enhancement without requiring complex overall redesign of the connection terminal structure

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The convex portions are pre-formed on the connection terminals before chip stacking, enabling improved mechanical strength to be achieved through a standardized manufacturing process rather than requiring complex assembly operations

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12469810B2Semiconductor package
Publication Date: 2025.11.11 SAMSUNG ELECTRONICS CO LTD
  • US12469810B2 patent drawing
  • US12469810B2 patent drawing
  • US12469810B2 patent drawing

AI summary

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region. Each of the connection terminals may include a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad. The convex portion may protrude in a direction away from a center of the first die. Protruding distances of the convex portions may increase in a direction from the center of the first die toward an outside of the first die.