Stacked Semiconductor Package Encapsulation for Interlayer Adhesion
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Solution Overview
Problem
The reliability of stacked semiconductor chips in semiconductor packages is a challenge due to the limitations of existing packaging technologies, which struggle to ensure effective electrical connection, mechanical protection, and thermal dissipation while maintaining a compact and lightweight design.
Innovation Solution
A semiconductor package design that incorporates through silicon vias (TSVs), conductive pads, conductive bumps, an interlayer adhesive layer, and an encapsulant to enhance the electrical and mechanical connection between stacked semiconductor chips, with the encapsulant extending into interlayer spaces to improve adhesion and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are stacked to reduce size and increase capacity, then the compactness and capacity are improved, but the reliability of electrical connection between chips deteriorates
Solution Approach 1:
The patent introduces an interlayer adhesive layer as an intermediary substance between stacked semiconductor chips. This adhesive layer fills the interlayer space and provides mechanical support and electrical connection stability, resolving the reliability issue that arises from compact stacking without excessive spacing.
Solution Approach 2:
The patent employs a composite structure combining multiple materials: conductive bumps for electrical connection, interlayer adhesive layer for mechanical bonding, and encapsulant for protection. This composite approach ensures both compact stacking and reliable electrical connections by leveraging the complementary properties of different materials.
2Volume of moving object
If interlayer space is reduced to improve compactness, then the volume is reduced, but the adhesion between chips deteriorates
Solution Approach 1:
The patent changes the physical and chemical parameters of the interlayer adhesive layer, including its viscosity, curing temperature, and composition ratios. By optimizing these parameters, the adhesive maintains strong bonding strength even in reduced interlayer spaces, resolving the contradiction between compactness and adhesion.
3Strength
If encapsulant is extended into interlayer space to improve adhesion, then the adhesion strength is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent merges the encapsulant formation process with the interlayer adhesive application process. The encapsulant is formed to extend into the interlayer space during the same packaging step, eliminating the need for separate processes and reducing manufacturing complexity while maintaining enhanced adhesion.
Data Source
AI summary
The reliability of stacked semiconductor packages may be improved via a semiconductor package including a first semiconductor chip including through silicon vias (TSVs) with respective upper conductive pads electrically connected to the TSVs, a second semiconductor chip on the first semiconductor chip with lower conductive pads on a lower surface of the second semiconductor chip, conductive bumps between the upper conductive pads and the lower conductive pads, and an interlayer adhesive layer between the first semiconductor chip and the second semiconductor chip. An interlayer space is between the first semiconductor chip and the second semiconductor chip and overlaps the first semiconductor chip and the second semiconductor chip in a vertical direction. The encapsulant extends into the interlayer space.