Stacked Semiconductor Package Interposer for Reliable Chip Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in achieving increased reliability due to limitations in interconnecting heterogeneous semiconductor chips effectively within a single package, which affects performance and capacity.
Innovation Solution
A semiconductor package design that includes a substrate with multiple semiconductor chips and an interposer chip, where each chip is electrically connected through through-vias and connection pads, allowing for direct bonding without additional connection members, enhancing the interconnection structure and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional connection members are used to interconnect semiconductor chips, then electrical connection reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the interconnection function into the substrate itself by forming conductive vias and pad structures directly on the substrate surface. This eliminates the need for separate connection members between chips, reducing device complexity while maintaining reliable electrical connections through the integrated substrate interconnection structure.
Solution Approach 2:
The substrate acts as an intermediary component that provides both mechanical support and electrical interconnection pathways. The conductive vias and pad structures on the substrate serve as intermediate connection points between different semiconductor chips, eliminating the need for additional connection members while ensuring reliable signal and power transmission.
2Productivity
If heterogeneous semiconductor chips are interconnected in a single package, then system capacity and performance are improved, but manufacturing precision and assembly difficulty increase
Solution Approach 1:
The substrate is designed with universal pad structures and conductive via patterns that can accommodate multiple types of semiconductor chips with different functions and pin configurations. This multi-functional interconnection approach enables heterogeneous chip integration without requiring custom connection solutions for each chip type, thereby improving system capacity while managing manufacturing complexity.
3Device complexity
If direct bonding without additional connection members is used, then device complexity is reduced, but electrical connection reliability may deteriorate
Solution Approach 1:
The patent combines the interconnection function directly into the substrate by forming conductive vias and pad structures on the substrate surface. This integration eliminates the need for separate connection members while maintaining reliable electrical connections through the substrate's own conductive pathways, thus reducing device complexity without compromising reliability.
Data Source
AI summary
A semiconductor package may include: a substrate; an upper chip disposed on the substrate; a first lower semiconductor chip disposed between the substrate and the upper chip, and electrically connected to the substrate; a second lower semiconductor chip disposed between the substrate and the upper chip, and electrically connected to the substrate; and an interposer chip disposed between the substrate and the upper chip, wherein the interposer chip includes a through-via electrically connecting the upper chip to the substrate, wherein the first lower semiconductor chip is electrically connected to the upper chip, wherein a lower surface of the upper chip is disposed on an upper surface of the first lower semiconductor chip, and wherein the second lower semiconductor chip is electrically connected to the upper chip, wherein a lower surface of the upper chip is disposed on an upper surface of the second lower semiconductor chip.