Stacked Semiconductor Package With Interposer Heat Path

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Solution Overview

Problem

Existing semiconductor packages face challenges in efficiently dissipating heat generated by semiconductor chips, which can lead to increased temperatures and potential operating failures.

Innovation Solution

A semiconductor package design that includes a stacked configuration of sub-devices with an interposer and a heat sink, utilizing thermal conductive layers, vias, and interface materials to facilitate efficient heat transfer and dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If semiconductor chips are mounted and operated, then functional performance is achieved, but heat is generated leading to increased temperature and potential operating failures

Engineering Contradiction:
Improveoperating reliabilityVSAvoidchip temperature
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent introduces thermal conductive vias and thermal conductive layers as intermediary structures between the semiconductor chip and the heat sink. These intermediaries facilitate efficient heat transfer from the chip through the interposer substrate to the heat sink, resolving the contradiction by providing a dedicated thermal conduction pathway that reduces chip temperature while maintaining operational reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent divides the thermal management system into multiple segmented components: thermal conductive vias for vertical heat transfer, thermal conductive layers for lateral heat distribution, and a heat sink for final heat dissipation. This segmentation allows optimized thermal management at different locations and levels, effectively controlling chip temperature while ensuring reliable operation

Inventive Principle:
Principle #1Segmentation

2Temperature

If thermal conductive vias are added to improve heat dissipation, then thermal performance is enhanced, but device complexity increases

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoidinterposer structure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The thermal conductive vias serve multiple functions: they provide thermal conduction pathways, act as structural support elements within the interposer, and can be integrated with existing electrical interconnect structures. This multi-functionality enhances heat dissipation while minimizing the increase in device complexity by reusing existing structural frameworks

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively reduces the temperature of semiconductor chips, preventing operating failures and enhancing the overall performance of the semiconductor package by improving thermal radiation.

Implementation Method 1

a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and a plurality of thermal conductive vias that penetrate the dielectric layer and connect the thermal conductive layer to the first thermal conductive pad

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

a heat sink covering the second sub-semiconductor device... capable of providing enhanced thermal radiation

Methodology Applied
Scientific EffectThermal radiation: Thermal Radiation

Data Source

PatentUS20250210533A1Semiconductor package
Publication Date: 2025.06.26 SAMSUNG ELECTRONICS CO LTD
  • US20250210533A1 patent drawing
  • US20250210533A1 patent drawing
  • US20250210533A1 patent drawing

AI summary

A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.