Stacked Semiconductor Package Interposer Layout for Testable Integration
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Solution Overview
Problem
The electronics industry faces challenges in integrating more circuits while reducing dimensions, enhancing performance, and improving functionality, requiring innovative semiconductor package structures that can efficiently connect and protect various chip structures.
Innovation Solution
A semiconductor package structure is developed, featuring a base plate with stacked semiconductor chips, an interposer layer with distinct interconnection regions, and a molding layer that seals the chip stack body and interposer layer, with a material layer on the sidewall for protection and flexibility in interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are stacked to increase integration, then circuit functionality and performance are improved, but manufacturing complexity and testing difficulty increase
Solution Approach 1:
The patent divides the semiconductor package into separate modular components: a base plate with first chips, an interposer layer, and a molding layer with second chips. This segmentation allows independent manufacturing and testing of each module before final assembly, reducing overall manufacturing complexity while maintaining high integration functionality.
Solution Approach 2:
The interposer layer serves as an intermediary component between the base plate and the molding layer. It provides electrical interconnection and mechanical support, enabling complex multi-chip integration while simplifying the manufacturing process by allowing separate assembly of chip stacks that are then connected through the interposer.
2Reliability
If a complete sealing structure is used to protect chips, then reliability against external factors is improved, but heat dissipation and electrical interconnection become difficult
Solution Approach 1:
The molding layer is designed with differentiated regions: a first region that is sealed to provide protection, and a second region that remains open to expose connection terminals for electrical interconnection. This local quality variation allows the same component to simultaneously provide both protection and electrical access without compromising either function.
3Productivity
If chips are packaged together as a single unit, then manufacturing efficiency is improved, but testing and failure analysis become more difficult
Solution Approach 1:
The package structure is segmented into a base plate portion and a molding layer portion that can be manufactured separately and then assembled. This allows each portion to be tested independently before final assembly, making failure analysis easier while still achieving efficient manufacturing through modular production processes.
Data Source
AI summary
A semiconductor package structure includes: a first base plate provided with a first surface; a first chip stack body located on the first base plate, where the first chip stack body includes a plurality of first semiconductor chips successively stacked onto one another in a direction perpendicular to the first base plate, and is electrically connected to the first surface of the first base plate; an interposer layer located on the chip stack body and provided with a first interconnection surface, where the first interconnection surface is provided with a first interconnection region electrically connected to the first base plate and a second interconnection region; and a molding layer configured to seal the first chip stack body, the interposer layer and the first surface of the first base plate. The first interconnection region is unsealed by the molding layer, and the second interconnection region is sealed by the molding layer.