Stacked Package Configurations for High IO Count Memory
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Solution Overview
Problem
Conventional package-on-package (PoP) integrated configurations face limitations in high Input/Output (IO) count due to space constraints, making it costly to implement through substrate vias (TSVs), which are not compatible with current business models for target capacity high IO memories.
Innovation Solution
The proposed solution involves a PoP integrated package configuration with multiple dies in stacked planes, using interconnects such as solder balls, pads, traces, and pillars to connect the dies without the need for TSVs, allowing for extended die portions to connect across planes and substrate interconnects, encapsulated by one or two mold layers for structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional PoP or side by side integrated packages are used, then the package structure is simple and manufacturing is easier, but the IO count is limited due to space constraints
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side package layout to a three-dimensional stacked configuration. Multiple memory dies are arranged in vertical planes (first plane, second plane, third plane) stacked above a substrate, enabling significantly higher IO counts by utilizing the vertical dimension. This stacking approach allows numerous interconnects to be distributed across multiple planes without increasing the substrate footprint area.
2Quantity of substance
If through substrate via (TSV) is implemented to achieve high IO count, then the IO capacity increases, but the manufacturing cost increases and compatibility with current business models decreases
Solution Approach 1:
The patent extracts and eliminates the TSV component from the package structure. Instead of using through-substrate vias to connect memory dies, the invention employs alternative interconnection methods such as bump bonds, wire bonds, or other interconnect structures that connect dies without requiring substrate penetration. This removal of TSVs reduces manufacturing complexity and cost while maintaining high IO count capabilities through the stacked die configuration.
3Quantity of substance
If more interconnects are added to increase IO count, then the memory capacity increases, but the device complexity and interconnection density increase
Solution Approach 1:
The patent segments the interconnection system into multiple independent planes (first plane, second plane, third plane), each containing a subset of the total interconnects. This segmentation distributes the interconnection density across multiple layers rather than concentrating all interconnects in a single plane. Each plane can be independently routed and managed, reducing the complexity of individual interconnection paths while achieving high aggregate memory capacity through the combined effect of all planes.
Data Source
AI summary
Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first plane, a second die located above the first die in a second plane with a portion extending past the first die, a third die located above the first die in the second plane with a portion extending past the first die, a fourth die located above the second die and the third die in a third plane with a portion extending past the second die and the third die, and a fifth die located above the second die and the third die in the third plane with a portion extending past the second die and the third die.