Stacked Semiconductor Package Layout for Higher I/O Density
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Solution Overview
Problem
Existing semiconductor package assemblies face challenges in arranging sufficient input/output (I/O) interfaces within the limited peripheral edges of a semiconductor die, particularly in package-on-package (POP) configurations.
Innovation Solution
The semiconductor package assembly includes a first semiconductor die with multiple interfaces arranged on its edges and a second semiconductor die stacked on top, utilizing conductive bumps and routing structures to establish electrical connections, allowing for more flexible interface design and increased I/O capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interfaces are arranged on the peripheral edges of the semiconductor die, then electrical connections can be established, but the number of I/O interfaces is limited by the available edge space
Solution Approach 1:
The patent transitions from arranging interfaces only on the peripheral edges (2D surface arrangement) to utilizing both edges and the central region of the semiconductor die (3D spatial utilization). By placing interfaces in the central region and using through-substrate vias to connect to conductive bumps on the opposite surface, the design effectively adds a vertical dimension to the interface arrangement, thereby increasing the total number of I/O interfaces without being constrained by the limited peripheral edge space.
2Quantity of substance
If multiple routing structures are stacked to increase I/O capacity, then more interfaces can be provided, but the device complexity increases
Solution Approach 1:
The patent divides the routing function into distinct segments: interface circuits in the central region, through-substrate vias for vertical connection, and conductive bumps on the opposite surface. This segmentation allows each component to be optimized independently and simplifies the overall routing architecture by eliminating the need for multiple stacked routing structures, thereby increasing I/O capacity while managing device complexity.
3Quantity of substance
If interfaces are placed closer to the edge to maximize space utilization, then more interfaces fit on the perimeter, but routing lengths increase and electrical performance deteriorates
Solution Approach 1:
By utilizing the central region of the die and implementing vertical connections through through-substrate vias and conductive bumps, the patent creates direct short-length signal paths that bypass the need for long peripheral routing. This three-dimensional approach allows interfaces to be positioned optimally in the central region while maintaining short electrical paths, thus maximizing both the number of interfaces and signal propagation speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the flexibility of interface design, increases the number of I/O interfaces, and improves the overall performance of the semiconductor package assembly by reducing routing lengths and optimizing power distribution.
Implementation Method 1
The second semiconductor die is electrically coupled to the first semiconductor die by the second interface... The semiconductor package assembly further includes a first conductive bump and a second conductive bump. The first conductive bump is disposed on the first surface of the first semiconductor die. The second conductive bump is disposed on the second surface of the first semiconductor die.
Data Source
AI summary
A semiconductor package assembly is provided. The semiconductor package assembly includes first and a second semiconductor dies. The first semiconductor die has a first surface and a second surface opposite the first surface. The first semiconductor die includes a first interface and a second interface. The second interface is arranged beside the first interface. The second interface is farther from the corresponding first edge of the first semiconductor die than the first interface. The second semiconductor die is stacked on the first semiconductor die. The semiconductor package assembly further includes a first conductive bump and a second conductive bump. The first conductive bump is disposed on the first surface of the first semiconductor die. The second conductive bump is disposed on the second surface of the first semiconductor die. The second semiconductor die is electrically coupled to the first semiconductor die by the second interface.