Stacked Semiconductor Package Layout for Dense I/O Isolation
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Solution Overview
Problem
As semiconductor chips become more compact and integrate multiple functions, they require a large number of input/output pads on a small area, posing challenges for structural stability and electrical properties in semiconductor packages.
Innovation Solution
A semiconductor package design featuring sequentially stacked wiring layers with a protection layer, dielectric layer, and substrate pads, where the dielectric layer is thinner than the dielectric patterns, and the upper substrate pads are thinner than the wiring patterns, reducing parasitic capacitance and allowing for improved electrical connections while maintaining a compact size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of input/output pads is increased to support multiple functions in compact semiconductor chips, then the functional integration is improved, but the structural stability and electrical properties deteriorate due to crowding and interference
Solution Approach 1:
The patent introduces a vertically stacked three-dimensional wiring structure with multiple wiring layers (first, second, and third wiring layers) connected through vertical conductors. This dimensional transition from planar to vertical interconnection allows numerous input/output pads to be arranged in a compact footprint while maintaining electrical isolation between signals through different layers, thus improving functional integration without compromising electrical properties
Solution Approach 2:
The patent employs dielectric layers as intermediary materials between adjacent wiring layers and between conductors. These dielectric layers provide electrical isolation and prevent short circuits between densely packed conductors, enabling high-density interconnection while maintaining reliable electrical properties. The dielectric material acts as a mediator that allows close proximity of conductors without direct contact
2Volume of moving object
If the thickness of the dielectric layer is reduced to achieve a compact package size, then the package volume is decreased, but the risk of electrical shorts between wiring layers increases
Solution Approach 1:
The patent utilizes composite dielectric structures with multiple dielectric layers having different material compositions and thicknesses. The first dielectric layer and second dielectric layer may have different dielectric constants and breakdown voltages, allowing optimization of space while maintaining electrical isolation. This composite approach enables compact packaging by reducing overall dielectric thickness in non-critical areas while preserving sufficient insulation in high-stress regions
3Quantity of substance
If the thickness of the upper substrate pad is reduced to accommodate more pads in limited space, then the pad density is increased, but the structural stability and current carrying capacity deteriorate
Solution Approach 1:
The patent compensates for reduced pad thickness by extending the pad structure into the vertical dimension through multi-layer stacking. Pads are formed across multiple wiring layers and connected through vertical conductors, distributing the mechanical and electrical load across three dimensions. This allows thinner individual pads while maintaining overall structural stability and current carrying capacity through the stacked configuration
Solution Approach 2:
The patent merges multiple pad functions into integrated pad structures that serve both as electrical connection points and as mechanical support elements. The substrate pads are combined with underlying support structures and dielectric layers to form composite pad assemblies that provide enhanced structural stability even when individual pad thickness is reduced to increase density
Data Source
AI summary
A semiconductor package includes stacked wiring layers, a lower substrate pad on a bottom surface of a lowermost wiring layer, a protection layer covering the lower substrate pad on the bottom surface of the lowermost wiring layer, a dielectric layer on a top surface of an uppermost wiring layer, an upper substrate pad on the dielectric layer, a semiconductor chip on the upper substrate pad, and a molding layer covering the semiconductor chip on the uppermost wiring layer. Each of the wiring layers includes a dielectric pattern and a wiring pattern therein. The protection layer has openings that expose the lower substrate pad. A thickness of the dielectric layer is less than that of the dielectric pattern in the wiring layers. A thickness of the upper substrate pad is less than that of the wiring pattern in the wiring layers.