Stacked Semiconductor Package Layout for I/O Interference Spacing
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Solution Overview
Problem
In semiconductor packages, the increased density of input/output (I/O) terminals leads to interference issues due to reduced distance between them, necessitating a solution to maintain reliability and compactness while preventing terminal interference.
Innovation Solution
A semiconductor package design incorporating a semiconductor chip with a lower redistribution structure, conductive posts, and a molding layer, where the conductive posts have a concave top surface and are integrated with a redistribution structure to increase the distance between I/O terminals, enhancing reliability and compactness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between I/O terminals is decreased to increase integration density, then the number of I/O terminals per unit area increases, but interference between I/O terminals occurs
Solution Approach 1:
The patent introduces a vertical dimension by stacking multiple semiconductor chips and redistribution structures in layers. I/O terminals are distributed across different vertical levels, allowing high terminal density while maintaining adequate spacing between terminals on the same layer to prevent interference.
Solution Approach 2:
The patent divides the I/O terminals into multiple groups located on different semiconductor chips and redistribution structures. By segmenting the terminal distribution across multiple discrete units stacked vertically, the patent achieves high overall terminal count while maintaining safe spacing within each segment to avoid interference.
2Volume of stationary object
If the semiconductor package size is reduced to make electronic components compact, then the volume decreases, but the distance between I/O terminals decreases leading to interference
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. By utilizing the vertical dimension for chip stacking and redistribution, the patent achieves compact package volume while maintaining adequate horizontal spacing between I/O terminals on each layer to prevent interference.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked within a compact package volume, with each chip containing I/O terminals. The redistribution structures and conductive posts are nested between the chips, achieving high terminal density in a small volume while maintaining terminal spacing through the vertical arrangement.
3Ease of manufacture
If conductive posts with convex top surfaces are used, then manufacturing is simplified, but the distance between I/O terminals is reduced increasing interference risk
Solution Approach 1:
The patent specifies that the top surface of the conductive post should be convex rather than flat. This curved geometry increases the effective distance between adjacent I/O terminals that contact the conductive post, reducing interference risk while still being compatible with standard manufacturing processes.
Data Source
AI summary
A semiconductor package includes: a lower package including a lower semiconductor chip, a molding layer on a side surface of the lower semiconductor chip, a conductive post in the molding layer and having a concave top surface, a lower redistribution pattern electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution electrically connected the conductive post; and an upper package on the lower package, the upper package including an upper semiconductor chip. A first portion of an inner wall of the molding layer contacts a sidewall of the conductive post, and a second portion of the inner wall of the molding layer extends vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post.