Stacked Semiconductor Package With Isolated Test Pads and Cu-Cu Bonding
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Solution Overview
Problem
The demand for compact, lightweight, and multifunctional semiconductor packages poses challenges in thermal properties and test functionality, particularly in stacking semiconductor chips using traditional Chip-on-Wafer methods, where heat dissipation is limited and test processes are cumbersome.
Innovation Solution
A semiconductor package is designed using a Die-to-Wafer method, where first and second semiconductor chips are bonded with Cu-Cu bonding, incorporating test pads and bonding pads to enhance thermal properties and facilitate testing, while maintaining electrical isolation of test pads from the second chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Chip-on-Wafer method is used to stack semiconductor chips, then storage capacity is increased, but thermal properties deteriorate due to limited heat dissipation
Solution Approach 1:
The patent divides the semiconductor structure into multiple separate chips (first semiconductor chip and second semiconductor chip) that are stacked vertically. Each chip maintains its own substrate and bonding pads, allowing independent thermal management. The segmentation enables heat to dissipate from multiple surfaces rather than being concentrated in a single integrated structure, thus improving thermal properties while maintaining high storage capacity through vertical stacking.
2Ease of manufacture
If traditional stacking methods are used, then manufacturing is simplified, but test functionality becomes cumbersome
Solution Approach 1:
The patent incorporates test pads on the first semiconductor chip before the stacking process. These test pads are preliminarily prepared and positioned to allow subsequent testing operations. By pre-configuring the test structure, the patent enables easy testing of the stacked device without requiring complex reconfiguration or additional manufacturing steps, thus improving test functionality while maintaining manufacturing simplicity.
3Volume of moving object
If semiconductor chips are stacked to reduce package size, then compactness is improved, but thermal dissipation becomes more difficult
Solution Approach 1:
The patent transitions from horizontal arrangement to vertical stacking, utilizing the third dimension (height) to reduce the footprint of the semiconductor package. Multiple chips are stacked in the vertical direction, which compresses the horizontal volume while creating additional thermal pathways through the vertical structure. The bonding pads and substrates in the stacked configuration provide multiple surfaces for heat dissipation, addressing the thermal management challenge inherent in compact vertical designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved thermal properties and facilitates efficient testing, addressing the limitations of traditional stacking methods by ensuring proper heat dissipation and enabling a compact, multifunctional semiconductor package with enhanced performance.
Implementation Method 1
bonded with Cu-Cu bonding
Data Source
AI summary
A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.