Stacked Semiconductor Package Bonding With Uniform Alignment Key Topology
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The die-to-wafer bonding process in multi-chip semiconductor packages faces challenges due to metal density differences between alignment key patterns and their surrounding regions, leading to degraded interfacial bonding quality and topology uniformity.
Innovation Solution
The semiconductor package design includes a first semiconductor chip with a first alignment key pattern on its surface, partially covered by a first passivation layer, and a second semiconductor chip with a second alignment key pattern on its back surface, also partially covered, allowing direct bonding of bonding pads and passivation layers, and using a die bonding apparatus for precise alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If alignment key patterns are formed on the die and wafer surfaces to facilitate die-to-wafer bonding, then alignment precision is improved, but metal density differences between the alignment key pattern and surrounding regions cause topology non-uniformity, worsening interfacial bonding quality
Solution Approach 1:
The patent applies local quality by forming a fill pattern in the background region surrounding the alignment key pattern. This fill pattern has the same material composition and metal density as the alignment key pattern itself, creating local uniformity in the bonding interface. The fill pattern is positioned adjacent to the alignment key pattern and extends to the edge of the bonding region, ensuring that the local metal density matches the surrounding areas, thereby preventing topology non-uniformity while preserving alignment precision.
2Device complexity
If direct pad-to-pad bonding is performed without solder bumps to achieve fine-pitch interconnection, then device complexity is reduced and integration density is improved, but bonding strength and reliability are worsened due to the absence of solder joints
Solution Approach 1:
The patent applies parameter changes by modifying the bonding process parameters, specifically the bonding temperature, to enable direct copper-to-copper bonding without solder. The bonding is performed at a temperature sufficient to activate diffusion bonding between the copper pads and copper alignment key patterns, achieving strong metallurgical bonds without requiring solder bumps. This changes the bonding mechanism from solder-based to direct metal diffusion, maintaining strength while reducing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances bonding quality by improving topology uniformity and preventing void generation, resulting in stronger, covalently bonded structures with improved bonding strength.
Implementation Method 1
aligning the first semiconductor chip and the second semiconductor chip using a first imaging portion on the lower support structure to image the second alignment key pattern and using a second imaging portion on the upper support structure to image the first alignment key pattern
Implementation Method 2
bonding the second semiconductor chip to the first semiconductor chip using a die bonding apparatus, such that the first bonding pad and the second bonding pad are directly bonded and the first passivation layer and the second passivation layer are directly bonded
Data Source
AI summary
A semiconductor package includes; a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes; a first substrate, a first bonding pad on a first surface of the first substrate, and a first passivation layer on the first surface of the first substrate exposing at least a portion of the first bonding pad. The second semiconductor chip includes; a second substrate, a second insulation layer on a front surface of the second substrate, a second bonding pad on the second insulation layer, a first alignment key pattern on the second insulation layer, and a second passivation layer on the second insulation layer, covering at least a portion of the first alignment key pattern, and exposing at least a portion of the second bonding pad, wherein the first bonding pad and the second bonding pad are directly bonded, and the first passivation layer and the second passivation layer are directly bonded.