Stacked Semiconductor Package Layout for High Capacity in Less Area
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving a small volume and large capacity while maintaining multiple functions, as they struggle to efficiently integrate multiple semiconductor chips without increasing the package size and complexity.
Innovation Solution
A semiconductor package design that includes a package redistribution layer, a cover insulating layer, lower and upper semiconductor chips, connection posts, and molding layers, allowing for efficient electrical connections and reduced horizontal area through specific chip arrangements and overlapping structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are integrated to increase capacity and functionality, then the package capacity and functionality are improved, but the package volume and horizontal area increase
Solution Approach 1:
The patent transitions from a planar arrangement of semiconductor chips to a three-dimensional stacked configuration. Multiple chips are arranged vertically across different levels (first level, second level, third level) and connected through vertical interconnect structures (through-mold vias, connection bumps). This dimensional change allows multiple chips to be integrated within a smaller horizontal footprint, effectively resolving the contradiction between increasing package capacity and minimizing horizontal area.
2Adaptability or versatility
If multiple semiconductor chips are integrated to enhance functionality, then the package functionality is improved, but the package structure becomes more complex
Solution Approach 1:
The patent divides the semiconductor package into distinct functional segments or modules. Each semiconductor chip represents an independent functional unit that can be designed, manufactured, and tested separately. The chips are then assembled in a stacked configuration with standardized interconnect interfaces. This segmentation allows for modular design, simplifying the overall package structure while enabling enhanced functionality through the combination of multiple specialized chips.
Solution Approach 2:
The patent implements a nested hierarchical structure where semiconductor chips are arranged in stacked levels, with each level containing functional units that are vertically integrated. The through-mold vias and connection structures create a nested interconnection system that passes through multiple layers, allowing signals and power to be routed between different functional levels. This nesting approach organizes complexity in a structured manner, making the multi-functional package more manageable.
3Area of stationary object
If chips are arranged to minimize horizontal area, then the package volume is reduced, but electrical connection reliability may deteriorate
Solution Approach 1:
The patent introduces intermediary connection structures to bridge the electrical connections between stacked semiconductor chips. Through-mold vias act as vertical intermediaries that penetrate the molding compound to establish electrical pathways between different chip levels. Connection bumps and pad structures serve as intermediate connection points that interface between chip electrodes and the vertical interconnects. These intermediary elements ensure reliable electrical connectivity while enabling the compact vertical arrangement that minimizes horizontal width.
Data Source
AI summary
A semiconductor package including a package redistribution layer, a cover insulating layer on the package redistribution layer; a lower semiconductor chip arranged between the package redistribution layer and the cover insulating layer and electrically connected to the package redistribution layer, a lower molding layer surrounding the lower semiconductor chip and filling between the package redistribution layer and the cover insulating layer, a plurality of connection posts electrically connected to the package redistribution layer by passing through the cover insulating layer and the lower molding layer, an upper semiconductor chip arranged above the cover insulating layer electrically connected to the plurality of connection posts, and an upper molding layer filling between the upper semiconductor chip and the cover insulating layer and surrounding the upper semiconductor chip may be provided.