Stacked Semiconductor Package Wiring for Low-Inductance Insulation
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Solution Overview
Problem
Existing semiconductor packages face challenges in reducing inductance while ensuring insulation distance between adjacent wires, leading to complications in current direction and increased magnetic flux, which can cause surge voltages and deterioration of power semiconductor elements.
Innovation Solution
A semiconductor package design featuring a first and second wiring layer with opposing current directions through insulating layers, reducing magnetic flux interference and inductance, while maintaining insulation and allowing for size reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wiring is routed to ensure insulation distance between adjacent wires, then insulation is maintained, but the wiring becomes complicated and inductance increases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked wiring layers. Multiple wiring layers are arranged vertically with insulating layers between them, allowing wires to pass through insulating layers via through-holes. This vertical arrangement reduces horizontal wiring complexity while maintaining insulation distances through the insulating layers.
Solution Approach 2:
The wiring structure is divided into multiple independent wiring layers separated by insulating layers. Each wiring layer can be independently designed and optimized, allowing simpler routing in each layer while the overall system achieves the required insulation through the stacked structure.
2Reliability
If the wiring is routed to ensure insulation distance between adjacent wires, then insulation is maintained, but inductance increases due to current in the same direction
Solution Approach 1:
By arranging wiring in multiple vertical layers, the patent enables current paths to be optimized independently in each layer. Currents can flow in opposite directions in adjacent layers, causing magnetic flux cancellation that reduces overall inductance while maintaining insulation through the insulating layers.
Solution Approach 2:
The patent converts the harmful magnetic flux effects into beneficial cancellation. By deliberately routing currents in opposite directions in adjacent wiring layers, the magnetic fluxes cancel each other out, transforming the potential harm of magnetic interference into a benefit of reduced inductance.
3Volume of moving object
If the package size is reduced, then weight and equipment size are reduced, but inductance reduction becomes more difficult
Solution Approach 1:
The patent uses vertical stacking of multiple wiring and insulating layers to achieve compact packaging. This three-dimensional arrangement reduces the horizontal footprint while providing sufficient space for current paths to be routed in opposite directions, enabling inductance reduction without increasing package size.
Solution Approach 2:
The patent implements a nested structure where wiring layers are embedded within insulating layers, which are in turn embedded within the package structure. This nested arrangement maximizes space utilization, allowing complex multi-layer wiring configurations to fit within a compact package volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively cancels out magnetic fluxes, reduces inductance, suppresses surge voltages, and enables smaller package size without compromising insulation or current capacity.
Implementation Method 1
the direction of current flowing through the portion of the second layer section overlying the first layer section of the first wiring layer is opposite to the direction of current flowing through the first layer section. Thus, the influences of magnetic fluxes by the current flowing through the first layer section and the current flowing through the second layer section can cancel each other out
Data Source
AI summary
A semiconductor package includes a semiconductor element, a first insulating layer, a first wiring layer, a second insulating layer, and a second wiring layer. The first insulating layer covers the semiconductor element. The first wiring layer includes a first layer section. The first layer section covers the first insulating layer. The second insulating layer covers the first insulating layer and the first wiring layer. The second wiring layer is electrically connected to the semiconductor element through a second through hole and a third through hole. The second wiring layer includes a second layer section. The second layer section covers the second insulating layer. The second layer section of the second wiring layer has a portion overlying the first layer section of the first wiring layer with the second insulating layer interposed.