Stacked Semiconductor Package Layout for More Memory Dies
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Solution Overview
Problem
There is a challenge in developing semiconductor packages that can efficiently increase performance and capacity while maintaining a reduced size, particularly in supporting a high number of memory dies with efficient data transmission speeds.
Innovation Solution
The semiconductor package design includes a package substrate with upper dies arranged non-overlapping vertically, electrical connection structures connecting the upper dies to the substrate, a lower die non-overlapping with the electrical connection structures, and overlapped electrical connection structures between the upper dies and the lower die, which are asymmetrically arranged to support the upper dies effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple upper dies are stacked vertically to increase capacity, then the number of memory dies increases, but the planar size increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from a conventional planar arrangement to a three-dimensional stacked configuration where multiple upper dies are vertically positioned above the lower die. This vertical stacking in the Z-dimension allows increasing the number of memory dies without expanding the X-Y planar footprint, directly resolving the contradiction between quantity and area.
Solution Approach 2:
The patent implements a nested structure where upper dies are positioned within the vertical projection area of the lower die, similar to nested dolls. The electrical connection structures extend through the lower die to connect upper dies, creating a compact nested arrangement that maximizes die density within the package footprint.
2Productivity
If electrical connection structures are added to connect multiple dies, then data transmission capability improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The electrical connection structures serve multiple functions simultaneously: they provide electrical pathways for data transmission between dies, act as mechanical support elements, and enable the vertical stacking architecture. This multi-functionality reduces the need for separate specialized components, thereby managing complexity while enhancing data transmission capability.
Solution Approach 2:
The patent introduces electrical connection structures as intermediary elements that mediate between the lower die and upper dies. These structures facilitate data transmission across the vertical interface, enabling high-speed communication while providing a standardized connection mechanism that simplifies the overall system architecture despite the increased number of connections required.
3Area of stationary object
If upper dies are arranged to overlap vertically with the lower die, then space utilization improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric arrangement of electrical connection structures within the vertical projection area. Rather than requiring perfectly symmetric alignment, the asymmetric design provides manufacturing tolerance and simplifies the alignment process while still achieving high space utilization. The connection structures are strategically positioned to optimize both space efficiency and manufacturability.
Data Source
AI summary
A semiconductor package may include a package substrate; a plurality of upper dies on an upper side of the package substrate and arranged so as not to overlap each other vertically; a plurality of electrical connection structures between the plurality of upper dies and the package substrate and electrically connected to the package substrate; a lower die on the package substrate and arranged so as not to vertically overlap with the plurality of electrical connection structures; and a plurality of overlapped electrical connection structures arranged between the plurality of upper dies and an upper surface of the lower die and electrically connected to the upper surface of the lower die. Each of the plurality of upper dies may include a plurality of memory dies that overlap each other vertically.