Stacked Semiconductor Package Layout for Custom High-Capacity Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently manufacturing customized semiconductor packages with stacked semiconductor chips that meet specific user demands, particularly in terms of high integration and large capacity.
Innovation Solution
A semiconductor package design involving multiple semiconductor chips with varying planar shapes and through electrodes, aligned in a vertical direction, and encapsulated by materials, allowing for efficient stacking and customization through modular primary packages and post-process integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to achieve high integration and large capacity, then the capacity and integration level are improved, but the manufacturing complexity and difficulty of meeting customized demands increase
Solution Approach 1:
The semiconductor package is divided into a modular structure where a first semiconductor chip (e.g., memory chip) is stacked on a second semiconductor chip (e.g., controller chip). This segmentation allows independent manufacturing and customization of each module, reducing overall manufacturing complexity while achieving high capacity through stacking.
Solution Approach 2:
The patent implements a nested structure where the first semiconductor chip is placed on top of the second semiconductor chip, with encapsulation material surrounding both chips. This nesting approach maximizes space utilization and capacity while maintaining a compact form factor that simplifies handling and assembly.
2Area of moving object
If semiconductor chips are stacked vertically to reduce footprint, then the area is reduced, but the alignment precision and manufacturing difficulty increase
Solution Approach 1:
The patent employs preliminary positioning structures such as protrusions on the first chip that fit into corresponding recesses on the second chip, and alignment marks prepared in advance during fabrication. These preliminary actions ensure precise vertical alignment before the actual stacking and encapsulation processes, reducing manufacturing difficulty.
Solution Approach 2:
Encapsulation material serves as an intermediary substance that fills the spaces between stacked chips and provides mechanical support and alignment stability. This intermediary material compensates for minor dimensional variations and ensures precise positioning of chips in the vertical stack.
3Adaptability or versatility
If customized semiconductor packages are manufactured to meet specific demands, then the adaptability is improved, but the productivity and manufacturing efficiency decrease
Solution Approach 1:
The patent designs a universal stacking architecture where the first and second semiconductor chips can represent different functional modules (memory, controller, buffer, etc.). This universal structure allows the same basic package design to be customized for different applications by simply changing the chip types or configurations, maintaining high productivity while achieving adaptability.
Solution Approach 2:
The patent enables customization through parameter changes such as varying the number of stacked chips, changing chip dimensions, adjusting encapsulation material properties, or modifying through-electrode configurations. These parameter adjustments allow tailored solutions for different demands without requiring complete redesign, thus preserving manufacturing efficiency.
Data Source
AI summary
Provided is a semiconductor package including a plurality of first semiconductor chips respectively including a first semiconductor substrate and a plurality of first through electrodes penetrating the first semiconductor substrate, a second semiconductor chip on the plurality of first semiconductor chips, the second semiconductor chip including a second semiconductor substrate and a plurality of second through electrodes penetrating the second semiconductor substrate, a third semiconductor chip on the second semiconductor chip, the third semiconductor chip including a third semiconductor substrate and a plurality of third through electrodes penetrating the third semiconductor substrate, and a first encapsulation material on the plurality of first semiconductor chips, a planar shape of the second semiconductor chip is greater than a planar shape of each first semiconductor chip of the plurality of first semiconductor chips, and a planar shape of the third semiconductor chip is greater than the planar shape of the second semiconductor chip.