3D Stacked Semiconductor Package for Dense Mixed-Device Integration
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Solution Overview
Problem
Current semiconductor package structures face challenges in achieving high circuit layout density and compatibility while maintaining a compact, lightweight design, due to complex packaging processes and limited integration of diverse device types.
Innovation Solution
A semiconductor package structure is developed with stacked sub-package bodies and interconnect structures that include molding bodies encapsulating passive and active devices, such as resistors, capacitors, inductors, transistors, and memory chips, allowing for electrical interconnection and enhanced heat dissipation through direct bonding and redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple device structures are integrated into a single package body, then circuit layout density increases, but device complexity increases
Solution Approach 1:
The package structure is divided into multiple sub-package bodies, each containing specific device structures (active devices, passive devices, or combinations). This segmentation allows for modular integration, reducing overall packaging complexity while maintaining high circuit layout density through systematic organization of devices across multiple sub-units.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by arranging multiple sub-package bodies vertically. This dimensional change enables higher circuit layout density without proportionally increasing packaging process complexity, as the modular sub-package approach allows for standardized assembly procedures.
2Adaptability or versatility
If multiple package bodies are stacked to increase integration, then device functionality increases, but package height increases
Solution Approach 1:
Multiple sub-package bodies are nested vertically within the overall package structure, with each sub-package containing encapsulated device structures. This nesting approach maximizes functional integration while minimizing the increase in package height through compact vertical stacking and efficient use of three-dimensional space.
3Adaptability or versatility
If diverse device structures are encapsulated in sub-package bodies, then compatibility increases, but manufacturing complexity increases
Solution Approach 1:
The sub-package body is designed as a universal encapsulation unit that can accommodate various device structures including active devices, passive devices, or combinations thereof. This multi-functional sub-package design increases package compatibility while reducing manufacturing complexity by standardizing the encapsulation process across different device types.
Data Source
AI summary
The present disclosure provides a semiconductor package structure, a fabrication method, and a memory system. The semiconductor package structure includes a plurality of package bodies stacked in a first direction. At least one of the plurality of package bodies includes first interconnect structures extending in the first direction and a plurality of sub package bodies stacked in the first direction. Each of the plurality of sub package bodies includes a molding body and a device structure encapsulated in the molding body. The device structure includes a passive device. The passive device includes at least one of a resistor, a capacitor, and an inductor.