Stacked Semiconductor Package Moat Structure Against Edge Cracks
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Solution Overview
Problem
In semiconductor packages with stacked chips, interfacial peeling or crack defects often occur at the edges of lower chips due to moisture absorption and expansion differences in high temperature and high humidity environments, especially in overhang regions where chip edges are not aligned.
Innovation Solution
The semiconductor package design includes a moat structure on the scribe lane regions of each chip, which extends along the edges of the chips to mitigate or prevent interfacial peeling or cracks from progressing from the chip edges into the chip interior, thereby reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chips are stacked in a cascade or zigzag manner to increase integration density, then productivity and device functionality are improved, but interfacial peeling and crack defects occur at edge portions due to moisture absorption and expansion differences
Solution Approach 1:
The patent divides the semiconductor substrate into distinct regions by forming moat structures (trenches) that segment the substrate into chip regions and scribe lane regions. This segmentation prevents crack propagation across the entire substrate by creating physical barriers at strategic locations, thereby resolving the contradiction between high integration density and reliability.
Solution Approach 2:
The patent applies different structural characteristics to different regions of the substrate. Moat structures are formed specifically in scribe lane regions adjacent to chip edges where stress concentration occurs during stacking. This localized structural modification addresses the reliability issue at critical locations without affecting the overall chip design and functionality.
2Reliability
If moat structures are formed on scribe lane regions adjacent to chip edges, then interfacial peeling and crack defects are reduced, but device complexity increases
Solution Approach 1:
The moat structures are formed during the substrate processing stage, before chip stacking and packaging. This preliminary action prevents potential reliability issues before they occur, eliminating the need for additional corrective measures or complex packaging structures later in the manufacturing process.
Solution Approach 2:
The moat structures create controlled porous or trench regions in the substrate that serve as stress relief zones. These structures are simple in form (trenches or grooves) but effective in function, providing crack prevention without requiring complex multi-layer or multi-material constructions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The moat structure effectively decreases the occurrence of interfacial peeling and crack defects in semiconductor packages by addressing the issues of moisture absorption and expansion, particularly in overhang regions where chip edges are not aligned.
Implementation Method 1
due to differences of moisture absorption and expansion of a molding member in the semiconductor package
Implementation Method 2
due to differences of moisture absorption and expansion of a molding member in the semiconductor package
Data Source
AI summary
A semiconductor package may include a package substrate including substrate pads, semiconductor chips stacked on an upper surface of the package substrate, bonding wirings electrically connecting the semiconductor chips and the substrate pads of the package substrate to each other; and a sealing member on the upper surface of the package substrate and covering the semiconductor chips. Each of the semiconductor chips may include a semiconductor substrate including a first edge and a second edge extending in a first direction and facing each other, a semiconductor chip region and a first scribe lane region and a second scribe lane region adjacent to the second edge, chip pad patterns on a portion of a semiconductor chip region of the semiconductor substrate adjacent to a first edge and along the first edge, and a moat structure on each of the first scribe lane region and the second scribe lane region.