Stacked Semiconductor Package With Through-Mold Via Interconnects
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high performance, high capacity, and high integration density, with issues related to reliability and durability, and there is a need to improve yield in the fabrication process.
Innovation Solution
A semiconductor package design featuring a first sub-package with a package substrate, a first chip, and a first mold layer, and a second sub-package with stacked chips and a second mold layer, interconnected by inner connection terminals with varying aspect ratios and widths, eliminating additional substrates between the sub-packages to enhance signal transmission speed and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional substrates are used between sub-packages for electrical connection, then reliability of connection is improved, but package thickness increases and signal transmission speed decreases
Solution Approach 1:
The patent extracts and eliminates the additional substrate layer between sub-packages, using only the necessary mold layers and inner connection terminals for electrical connection. This removes unnecessary structural elements that increase package thickness while maintaining connection functionality through the streamlined configuration of mold vias and connection terminals.
Solution Approach 2:
The patent transitions from a planar substrate-based connection approach to a vertical through-mold via connection approach. By using mold vias that penetrate through the mold layers in the vertical dimension, the patent achieves electrical connection without requiring additional horizontal substrate layers, thereby reducing package thickness.
2Reliability
If additional substrates are used between sub-packages, then electrical connection is achieved, but signal transmission speed decreases
Solution Approach 1:
The patent removes additional substrate layers that would introduce signal delay, keeping only the essential mold layers and connection terminals. This extraction of unnecessary intermediate layers reduces the signal path length and eliminates additional interfaces that could degrade signal transmission speed.
3Reliability
If multiple substrates are used in the package structure, then electrical connection and structural support are improved, but heat dissipation performance deteriorates
Solution Approach 1:
The patent extracts and eliminates additional substrate layers that act as thermal barriers, reducing the number of interfaces and material layers that impede heat flow. The streamlined structure with fewer intermediate layers allows more efficient heat dissipation from the chips to the external environment.
4Ease of manufacture
If conventional substrate-based connection is used, then fabrication process is simplified, but integration density and capacity are limited
Solution Approach 1:
The patent employs vertical stacking of chips connected through mold vias in the thickness direction, transitioning from planar integration to three-dimensional integration. This dimensional change enables higher integration density by utilizing the vertical space within the package, accommodating more chips and connections without increasing the package footprint.
5Reliability
If mold vias with large aspect ratio are used, then electrical connection through mold layers is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the geometric parameters of mold vias, including diameter, depth, and aspect ratio, to achieve reliable electrical connection while managing manufacturing precision requirements. By carefully controlling via dimensions and using appropriate filling materials, the patent balances connection reliability with manufacturability.
Data Source
AI summary
A semiconductor package includes a first sub-package, a second sub-package on the first sub-package, and a first inner connection terminal between the first and second sub-packages to electrically connect them to each other. The first sub-package includes a package substrate, a first chip on the package substrate, a first mold layer covering the package substrate and the first chip, and a first mold via provided next to the first chip to penetrate the first mold layer. The second sub-package includes second chips sequentially stacked to be offset from each other, the second chips including chip pads exposed through bottom surfaces thereof, a second mold layer covering the second chips, and a second mold via penetrating a portion of the second mold layer and contacting a chip pad of the uppermost one of the second chips. The first inner connection terminal contacts the first and second mold vias.