Stacked Semiconductor Package Layout for Thin Multi-Chip Assembly
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Solution Overview
Problem
The increasing demand for compact and multifunctional electronic products necessitates the development of semiconductor packages with smaller volumes that can accommodate multiple semiconductor chips while maintaining various functions.
Innovation Solution
A semiconductor package design featuring a package substrate with a substrate base, wiring patterns, a lower semiconductor chip, and an upper semiconductor chip, where the lower chip is embedded in a chip-accommodating cavity and connected via bonding wires, and the upper chip is attached across the lower chip with adhesive films, reducing the overall thickness and volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are mounted on a substrate, then the functionality of the electronic product is enhanced, but the volume of the semiconductor package increases
Solution Approach 1:
The patent transitions from planar mounting to three-dimensional stacking, placing semiconductor chips at different vertical levels (first chip at first level, second chip at second level). This dimensional change allows multiple chips to be integrated without increasing package footprint, resolving the contradiction between enhanced functionality and increased volume.
Solution Approach 2:
The patent implements a nested structure where the second semiconductor chip is positioned to overhang the first chip, and both are integrated within the substrate cavity. This nesting arrangement maximizes space utilization, allowing multiple chips to coexist in a compact vertical configuration rather than requiring additional horizontal space.
2Volume of stationary object
If the substrate base thickness is reduced to minimize package volume, then the package size is reduced, but the structural reliability and warpage control deteriorate
Solution Approach 1:
The substrate base is segmented into functional regions: a cavity region accommodating the chips and a support region providing structural integrity. This segmentation allows the cavity area to be optimized for compactness while the support region maintains sufficient thickness for reliability, resolving the contradiction between reduced package size and maintained structural reliability.
Solution Approach 2:
Different regions of the substrate base are assigned different thickness characteristics: thinner regions under the chips for compactness and thicker regions at the periphery for structural support and warpage control. This local quality differentiation allows the package to achieve small overall volume while maintaining reliability through strategically positioned structural reinforcement.
3Volume of stationary object
If the chip-accommodating cavity is designed to fit chips tightly, then the package volume is reduced, but the assembly precision and alignment difficulty increase
Solution Approach 1:
The cavity dimensions and chip positions are predetermined during substrate fabrication, with pre-formed bonding pads and alignment features. This preliminary action establishes precise reference points before chip mounting, enabling accurate chip placement and wiring alignment while maintaining compact cavity dimensions, thus resolving the contradiction between reduced volume and maintained assembly precision.
Data Source
AI summary
A semiconductor package includes a package substrate which includes a substrate base and a plurality of wiring patterns, a lower semiconductor chip, and an upper semiconductor chip. The substrate base includes a chip-accommodating cavity and the plurality of wiring patterns include a plurality of bottom wiring patterns on a bottom surface of the substrate base and a plurality of top wiring patterns on a top surface of the substrate base. The lower semiconductor chip is disposed in the chip-accommodating cavity and is connected to the plurality of bottom wiring patterns through a plurality of lower bonding wires. The upper semiconductor chip includes a first portion which is attached to the lower semiconductor chip and a second portion which overhangs the lower semiconductor chip.