Stacked Semiconductor Package Structure Without Cu-Cu Bonding
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Solution Overview
Problem
Existing semiconductor package structures face challenges with high manufacturing costs and difficulties due to copper-copper (Cu—Cu) bonding technology, which requires high temperature and time for inter-diffusion, leading to process complexities and reduced yield.
Innovation Solution
The semiconductor package structures utilize a redistribution layer and conductive pillars or bump structures to connect semiconductor components, replacing Cu—Cu bonding, thereby simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper-copper (Cu—Cu) bonding technology is utilized to provide interconnections between semiconductor dies, then reliable electrical connections are achieved, but high temperature and time for inter-diffusion are required, which raises manufacturing cost and leads to process difficulties
Solution Approach 1:
The patent introduces an intermediary material layer between the copper interconnect structures of different semiconductor dies. This intermediary layer facilitates electrical connection without requiring direct Cu-Cu bonding, thereby eliminating the need for high temperature and extended time for inter-diffusion while maintaining reliable electrical connections. The intermediary material acts as a mediator that simplifies the manufacturing process by removing the complex thermal bonding requirements.
2Reliability
If copper-copper (Cu—Cu) bonding technology is utilized to provide interconnections between semiconductor dies, then reliable electrical connections are achieved, but the manufacturing cost increases and yield decreases
Solution Approach 1:
The intermediary material layer enables electrical connections to be formed without the complex Cu-Cu bonding process, thereby improving manufacturing yield by reducing process variability and defects associated with high temperature bonding. This approach allows for more controlled and repeatable fabrication processes, directly impacting productivity and yield enhancement.
3Area of stationary object
If smaller package structures are designed to take up less space, then space efficiency is improved, but integration of multiple semiconductor dies becomes more challenging
Solution Approach 1:
The patent implements a stacked package architecture where multiple semiconductor dies are vertically integrated one above another, similar to nested dolls. This three-dimensional arrangement allows multiple functional components to be housed within a compact footprint, achieving space efficiency while managing integration complexity through vertical rather than lateral expansion. The intermediary material layers facilitate this nested configuration by enabling electrical connections between stacked dies.
4Productivity
If heterogeneous integration of multiple semiconductor dies is implemented, then manufacturing cost is reduced and high performance is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The intermediary material layer serves as a universal interface that simplifies heterogeneous integration by providing a standardized connection method between different types of semiconductor dies. Rather than requiring specific bonding procedures for each die combination, the intermediary material enables straightforward integration, reducing process complexity while maintaining the cost and performance benefits of heterogeneous architectures.
Data Source
AI summary
A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.