Stacked Semiconductor Package Without Silicon Interposers
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Solution Overview
Problem
The challenge is to develop a semiconductor package that integrates multiple semiconductor chips while minimizing size and maximizing functionality, particularly in compact electronic devices.
Innovation Solution
The semiconductor package includes a first semiconductor chip with a substrate, through electrodes, and connection pads, stacked with multiple second semiconductor chips, bonded using wires, and encapsulated in a molding layer, with external connection terminals on the lower surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated in a compact package, then functionality and data bus width are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The semiconductor package is divided into multiple discrete chip layers (first semiconductor chip, second semiconductor chips) that can be manufactured separately and then stacked. This segmentation allows each chip to be optimized independently while achieving high functionality when combined, resolving the contradiction between versatility and manufacturing complexity.
Solution Approach 2:
Multiple semiconductor chips are stacked vertically in a nested configuration where second semiconductor chips are positioned on top of the first semiconductor chip. This nesting approach maximizes functionality within a compact volume while using standardized stacking processes that don't significantly increase manufacturing complexity.
2Productivity
If multiple semiconductor chips are stacked to increase data bus width, then bandwidth is improved, but package size increases
Solution Approach 1:
Instead of expanding the package horizontally to accommodate more chips for increased bandwidth, the design transitions to vertical stacking in the third dimension. Multiple semiconductor chips are arranged in layers above and below the first chip, achieving wide data bus width (e.g., 128 bits) while maintaining a compact footprint area.
3Ease of manufacture
If bonding wires are used to connect chips, then manufacturing cost is reduced, but connection reliability may be affected
Solution Approach 1:
A molding layer is introduced as an intermediary component that encapsulates the bonding wires and provides mechanical support and protection. This mediator shields the vulnerable wire bonds from external stresses while maintaining electrical connectivity, thus preserving reliability without sacrificing the cost advantages of wire bonding.
4Manufacturing precision
If silicon interposers are used for chip integration, then connection precision is improved, but manufacturing cost increases significantly
Solution Approach 1:
The design replaces expensive silicon interposers with a cost-effective organic substrate that performs the necessary interconnection function. The organic substrate, while less durable than silicon, provides sufficient precision for chip-to-chip connections at a fraction of the cost, making it an economically viable alternative for achieving manufacturing precision.
Data Source
AI summary
A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.