Stacked Semiconductor Package Layout for Lower Overhang and Height
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Solution Overview
Problem
In semiconductor packages, the diagonal stacking of chips leads to an overhang portion that can bend and increase the package height, along with the need for more conductive wires for electrical connections.
Innovation Solution
The semiconductor package design includes a package substrate with stacked semiconductor chips, where each chip has specific pads and wirings arranged in horizontal directions, with subsequent chips stacked to cover sub-chip pads, reducing overhang and the number of conductive wires needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If semiconductor chips are stacked in a stepped shape to be tilted diagonally to expose chip pads for wire bonding, then chip pads are exposed for electrical connection, but the overhang portion easily bends and the package height increases
Solution Approach 1:
Instead of tilting chips diagonally to expose pads, the patent inverts the approach by arranging chips in a stepped shape along orthogonal directions (first and second horizontal directions) with pads exposed in respective directions, eliminating the need for diagonal tilting while maintaining pad accessibility for wire bonding
Solution Approach 2:
The patent transitions from diagonal tilting in one dimension to orthogonal stepped stacking in multiple dimensions (first horizontal direction and second horizontal direction perpendicular to the first), allowing pads to be exposed in different orientations without requiring chip tilting, thereby reducing overhang and improving stability
2Ease of operation
If semiconductor chips are stacked in a stepped shape to be tilted diagonally to expose chip pads, then chip pads are exposed for wire bonding, but the height of the semiconductor package increases
Solution Approach 1:
The patent inverts the conventional diagonal tilting approach by using orthogonal stepped stacking where chips are arranged in first and second horizontal directions, allowing pad exposure without vertical height increase from tilting, thus reducing overall package height while maintaining wire bonding accessibility
3Reliability
If multiple conductive wires are used to electrically connect chip pads and substrate pads, then electrical connection is achieved, but the package height increases
Solution Approach 1:
The patent merges multiple wire bonding operations into a more compact arrangement by orthogonal stepped stacking, where connection lines can be routed more efficiently through the stepped structure, reducing the vertical space required for electrical connections and thereby reducing package height while maintaining connection reliability
Data Source
AI summary
A semiconductor package includes a package substrate having a plurality of substrate pads, a first semiconductor chip stacked on the package substrate and having a plurality of first chip pads and first option pads along a first horizontal direction, a plurality of first sub-chip pads along a second horizontal direction, and a plurality of first wirings electrically connecting the first chip pads and the first sub-chip pads, a second semiconductor chip stacked on the first semiconductor chip to cover the first sub-chip pads, and having a plurality of second chip pads and second option pads along the first horizontal direction, a plurality of second sub-chip pads along the second horizontal direction, and a plurality of second wirings electrically connecting the second chip pads and the second sub-chip pads, and a plurality of connection lines electrically connecting the package substrate and the first and second semiconductor chips.