Stacked Semiconductor Package Pad Offset for Thermal Deformation
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Solution Overview
Problem
The increasing demand for miniaturized and lightweight electronic components, particularly in portable devices, requires advanced semiconductor package technologies that can integrate multiple devices while maintaining excellent electrical characteristics and handling high-frequency signals effectively.
Innovation Solution
A semiconductor package design featuring a substrate with multiple semiconductor chips stacked in a specific offset structure, where the alignment of chip stack pads and bonding layers allows for efficient electrical connections and reduced thickness, enhancing reliability and minimizing damage from external deformations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are stacked vertically to achieve miniaturization, then the package size is reduced, but thermal deformation and repulsive forces increase causing reliability issues
Solution Approach 1:
The patent applies asymmetry by intentionally misaligning the centers of chip stack pads in adjacent semiconductor chips. Instead of perfect vertical alignment, the pads are offset by a predetermined distance, creating an asymmetric configuration that reduces repulsive forces during thermal deformation while maintaining electrical connectivity through wire bonds.
Solution Approach 2:
The patent transitions from one-dimensional vertical stacking with perfect alignment to a two-dimensional offset arrangement. By introducing horizontal misalignment in addition to vertical stacking, the design creates space for wire bonds to connect pads without experiencing excessive repulsive forces during thermal expansion and contraction.
2Ease of manufacture
If chip stack pads are perfectly aligned vertically for compact design, then manufacturing is simplified, but repulsive forces during thermal deformation damage electrical connections
Solution Approach 1:
The patent applies preliminary anti-action by pre-positioning the chip stack pads at misaligned centers before thermal deformation occurs. This predetermined offset creates initial spacing that counteracts the repulsive forces generated during thermal expansion and contraction, preventing damage to wire bonds and electrical connections before the harmful forces can act on them.
3Reliability
If wire bonds are made long to connect misaligned pads, then electrical connection reliability improves, but inductance increases degrading high-frequency signal characteristics
Solution Approach 1:
The patent applies parameter changes by optimizing the misalignment distance between chip stack pads to a predetermined value. This specific distance parameter balances two competing requirements: it is large enough to reduce repulsive forces on wire bonds during thermal deformation, yet small enough to keep wire bond lengths short and inductance low for maintaining high-frequency signal characteristics.
Data Source
AI summary
A semiconductor package includes a substrate, a substrate pad on an upper surface of the substrate, first and second semiconductor chips stacked on the substrate in a first direction, wherein a sidewall of the first semiconductor chip and a sidewall of the second semiconductor chip are on the same plane, a first chip stack pad on an upper surface of the first semiconductor chip, a second chip stack pad on an upper surface of the second semiconductor chip, a first wire connecting the first chip stack pad with the substrate pad, and a second wire connecting the second chip stack pad with the substrate pad, wherein a first center of an upper surface of the first chip stack pad and a second center of an upper surface of the second chip stack pad are misaligned in the first direction.