Stacked Semiconductor Package Pad Layout for Warpage Resistance
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Solution Overview
Problem
Semiconductor packages face warpage issues due to thermal expansion coefficient differences, leading to instability and potential bending, particularly in stacked configurations where corner areas may be weak and prone to heat-induced deformation.
Innovation Solution
A semiconductor package design featuring a first and second semiconductor chip with specific pad configurations and a fillet layer, where the second chip's bottom surface is convex, and through electrodes connect pads across chips, with a molding member covering the structure to enhance adhesion and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are stacked on a single package wiring structure, then functional integration and compactness are improved, but warpage phenomenon occurs due to thermal expansion coefficient differences
Solution Approach 1:
The patent applies local quality by creating pads with different heights at different locations on the chip. Specifically, first pads have a first height while second pads have a second height that is greater than the first height. This localized variation in pad height compensates for the warpage caused by thermal expansion differences, allowing the package to maintain stability while achieving high functional integration through chip stacking.
2Ease of manufacture
If corner areas of semiconductor package are made weaker to allow bending, then ease of assembly is improved, but warpage resistance deteriorates
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for the expected warpage through the differential pad height design. The second pads, which are located in corner areas and have greater height than first pads, are designed in advance to counteract the upward bending force that will occur during heating. This allows the corner areas to remain relatively weak for assembly ease while simultaneously providing warpage resistance through the pre-engineered height compensation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves adhesion and connection stability between chips, compensates for distance variations, and facilitates even attachment, reducing warpage and enhancing overall package reliability.
Implementation Method 1
A fillet layer is between the first and second semiconductor chips and surrounds the plurality of first pads, the plurality of second pads, the plurality of third pads and the plurality of fourth pads
Implementation Method 2
The second bottom surface is convex. A distance between bottom surfaces of the plurality of first pads and the second bottom surface is less than a distance between bottom surfaces of the plurality of second pads and the second bottom surface
Implementation Method 3
a molding member covering the first semiconductor chip, the second semiconductor chip, and the fillet layer
Data Source
AI summary
A semiconductor package includes a first semiconductor chip having a first top surface and an opposite first bottom surface, first pads on the first top surface, each having a first width and a first height, second pads on the first top surface further outward from a center of the first semiconductor chip, each having a second width less than the first width and a second height greater than the first height. The semiconductor package further includes a second semiconductor chip having a second bottom surface which faces the first top surface and an opposite second top surface, third pads on the second bottom surface which are connected to the first pads, and fourth pads on the second bottom surface which are connected to the second pads. The second bottom surface is convex.