Stacked Semiconductor Package With Patterned Chip Interconnects
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Solution Overview
Problem
Conventional semiconductor packages with stacked semiconductor chips face thickness and manufacturing complexity issues due to wire bonding, necessitating a more efficient electrical connection method.
Innovation Solution
A semiconductor package design that connects stacked semiconductor chips through conductive patterns formed by patterning, allowing for a zig-zag stacking configuration and eliminating the need for wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to establish electrical connections between stacked semiconductor chips and package substrate, then electrical connectivity is achieved, but package thickness increases and manufacturing process complexity increases
Solution Approach 1:
The patent transitions from three-dimensional wire bonding (requiring wire loops to reach from chip to substrate) to two-dimensional planar conductive patterns that extend laterally along chip surfaces and substrate, eliminating the need for vertical wire traversal and reducing package thickness
Solution Approach 2:
The patent extracts and eliminates the wire bonding process entirely, replacing it with integrated conductive patterns that are formed through patterning processes directly on the chip and substrate surfaces, removing the intermediate wire connection layer
2Reliability
If wire bonding is used to establish electrical connections between stacked semiconductor chips and package substrate, then electrical connectivity is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the electrical connection function into the existing patterning and fabrication processes of the semiconductor chips and package substrate, eliminating the need for separate wire bonding equipment and process steps
Solution Approach 2:
The patent replaces the mechanical wire bonding process (requiring wire feeders, bonding heads, and precise positioning) with photolithography-based patterning processes that are already standard in semiconductor manufacturing
3Quantity of substance
If multiple semiconductor chips are stacked to achieve larger capacity, then storage capacity increases, but package thickness increases
Solution Approach 1:
The patent enables more aggressive chip stacking by replacing thick wire bonds with thin planar conductive patterns, allowing chips to be positioned closer together vertically while maintaining electrical connectivity through lateral pattern extensions
Data Source
AI summary
An example semiconductor package includes a package substrate including a first upper connection pad and a second upper connection pad on a top surface of the package substrate, a first semiconductor chip stack including a plurality of first semiconductor chips and a first chip pad, a second semiconductor chip stack including a second chip pad and a plurality of second semiconductor chips stacked in a step-like shape on the first semiconductor chip stack, a first conductive pattern extending on the first semiconductor chip and the package substrate, a first cover insulation layer covering at least a portion of the first conductive pattern, a first encapsulation member surrounding the first semiconductor chip stack and the first conductive pattern, and a second conductive pattern extending along the second semiconductor chip, the first encapsulation member, and the package substrate.