Stacked Semiconductor Package with Penetration Vias for Thin Interconnects
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving efficient operation and reduced thickness due to the use of bulk silicon substrates, which increase package thickness and hinder operational efficiency.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip with a first penetration via and a second semiconductor chip with a second penetration via, connected through a third penetration via, allowing for efficient electrical connection and reduced thickness. The chips are stacked with a third semiconductor chip on top, forming a hybrid bonding structure for improved stability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If bulk silicon substrates are used in semiconductor packages, then structural stability is improved, but package thickness increases and operational efficiency deteriorates
Solution Approach 1:
The patent divides the semiconductor package into multiple discrete chips (first semiconductor chip, second semiconductor chip, third semiconductor chip) stacked vertically, eliminating the need for a single bulky substrate. Each chip is connected through penetration vias, achieving both reduced thickness and maintained structural stability through modular segmentation.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout on a bulk substrate to a three-dimensional vertical stacking architecture. Chips are arranged in multiple layers connected via vertical penetration vias, reducing the horizontal footprint and overall package thickness while maintaining electrical connectivity through the third dimension.
2Reliability
If penetration vias with varying widths and heights are used, then electrical connection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different via dimensions at different locations and levels: the first penetration via has a first width and first height, while the second penetration via has a second width larger than the first width and a second height larger than the first height. This local variation optimizes electrical connection efficiency for specific routing needs while maintaining overall manufacturing feasibility through systematic progression rather than random complexity.
Data Source
AI summary
A semiconductor package includes a first chip and a second chip disposed thereon. The first chip includes a first semiconductor substrate including first and second surfaces, a first circuit layer disposed on the first surface, a first interconnection layer disposed on the first circuit layer, the first interconnection layer including a landing pad, a second interconnection layer disposed on the second surface, and a first penetration via protruding from the second interconnection layer and penetrating the first semiconductor substrate. The second chip includes a second semiconductor substrate including third and fourth surfaces, the fourth surface being closer to the first chip than the third surface, a third interconnection layer disposed on the fourth surface, a second circuit layer disposed between the third interconnection layer and the fourth surface, and a second penetration via penetrating the second semiconductor substrate and connected to the landing pad.