Stacked Electronic Package Layout for Photonic Chip Miniaturization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to the large layout area occupied by adjacently arranged switch die and light engine modules, hindering multi-pin connections and high functionality.
Innovation Solution
The electronic package integrates a photo IC into the carrier structure and integrates a switch die into the electronic module, reducing the layout area by embedding the photo IC and stacking the elements to minimize substrate space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If switch die and light engine module are adjacently arranged on package substrate, then electrical connections and optical connections can be established, but layout area of package substrate becomes large
Solution Approach 1:
The patent transitions from a planar arrangement where switch die and light engine module are placed side-by-side on the package substrate to a vertical stacked arrangement. The active device is positioned above the passive device, utilizing the third dimension (height) to reduce the footprint on the package substrate while maintaining all necessary electrical and optical connections through vertically oriented conductive structures.
Solution Approach 2:
The patent employs a nested configuration where the active device (switch die) and passive device (light engine module) are stacked vertically, with each device containing its own internal structures and interconnections. The active device is positioned within the vertical space above the passive device, creating a compact nested arrangement that minimizes the overall layout area while preserving functional integrity.
2Adaptability or versatility
If large layout area is used for switch die and light engine module, then multi-pin connections can be accommodated, but miniaturization requirement cannot be met
Solution Approach 1:
The patent utilizes vertical stacking to accommodate multiple pins and connections in the height dimension rather than spreading them out horizontally. Conductive pillars and interconnection structures are arranged vertically to provide multi-pin connectivity between the stacked devices, enabling high-density interconnection without increasing the package substrate footprint.
Solution Approach 2:
The patent changes the spatial distribution parameter from horizontal dispersion to vertical concentration. By transforming the arrangement from a two-dimensional planar layout to a three-dimensional stacked configuration, the system maintains multi-pin connection capability while significantly reducing the area parameter of the package substrate.
Data Source
AI summary
An electronic package is provided, in which an electronic module including a first electronic element and a second electronic element is disposed on a carrier structure embedded with a third electronic element, and the third electronic element is a photonic chip electrically connected to the electronic module. Therefore, with this configuration, it is beneficial to reduce a layout area of the carrier structure to meet the requirement of miniaturization.