Stacked Package Design with Planarized Chips for High Density
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Solution Overview
Problem
Current semiconductor packaging technologies face limitations in increasing memory capacity and mounting density due to constraints in the number of stacked chips, leading to inefficiencies in area utilization and reliability.
Innovation Solution
A stacked package design featuring a substrate with connection pads, a first semiconductor chip mounted in flip-chip bonding, a first adhesive member covering the chip, and a second semiconductor chip with bumps bonded to the substrate pads, along with planarization of the second chip's surface, allowing for increased chip stacking and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor packaging is used, then manufacturing process is simple, but memory capacity and mounting density cannot be increased
Solution Approach 1:
The patent transitions from conventional planar packaging to three-dimensional stacked packaging. Multiple semiconductor chips are vertically stacked and bonded together, utilizing the vertical dimension to increase memory capacity and mounting density without expanding the horizontal footprint. This dimensional change enables higher integration while maintaining a compact form factor.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked one on top of another, with each chip containing functional elements. The chips are nested vertically through bonding interfaces, creating a compact hierarchical structure that maximizes space utilization and increases overall capacity within a limited volume.
2Quantity of substance
If more chips are stacked, then memory capacity increases, but mounting reliability deteriorates
Solution Approach 1:
The patent applies preliminary planarization processing to the upper surface of each stacked chip before bonding to the next chip. This preliminary action ensures that each bonding interface starts with a flat surface, preventing cumulative surface irregularities that would compromise reliability. By addressing surface flatness in advance, the bonding quality and overall mounting reliability are maintained even as the number of stacked chips increases.
Solution Approach 2:
The patent modifies the surface flatness parameter of each chip through planarization processing before stacking. This parameter change ensures that each bonding interface meets specific flatness requirements, which is critical for reliable bonding. By controlling and optimizing the surface flatness parameter, the patent maintains high mounting reliability across multiple stacked chips.
3Area of stationary object
If chip stacking is increased, then area utilization improves, but surface flatness deteriorates
Solution Approach 1:
The patent performs planarization processing on the upper surface of each chip before stacking to preliminarily ensure surface flatness. This preliminary action prevents surface irregularities from accumulating through the stack, maintaining manufacturing precision even as the number of stacked chips increases and area utilization improves.
Solution Approach 2:
The patent actively controls and modifies the surface flatness parameter through planarization processing. By adjusting and optimizing this parameter before each bonding step, the patent maintains high manufacturing precision across the entire stacked structure while maximizing area utilization through increased chip stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances memory capacity and mounting density by enabling more chips to be stacked securely, preventing defects and improving wire bonding, thus overcoming limitations in existing technologies.
Implementation Method 1
a first adhesive member that covers a portion of the upper surface of the substrate including the first semiconductor chip
Implementation Method 2
the bumps are bonded to the connection pads
Data Source
AI summary
The stacked package includes: a substrate having an upper surface formed with connection pads, a lower surface, and four side surfaces; a first semiconductor chip mounted over the upper surface of the substrate; a first adhesive member that covers a portion of the substrate including the first semiconductor chip; and a second semiconductor chip formed with bumps on edges of a first surface and mounted over the substrate with interposition of the first semiconductor chip and the first adhesive member such that a center of the first surface is attached over the first adhesive member and the bumps are bonded onto the connection pads, with a second surface opposing to the first surface being polished evenly.