Stacked Semiconductor Package Interconnects for Compact Power Delivery
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved electrical characteristics and structural stability while maintaining a small size, particularly in responding to the demand for high functionality, high speed, and miniaturization.
Innovation Solution
The semiconductor package incorporates a lower redistribution layer with a first semiconductor chip, a second semiconductor chip stacked on the first, under-bump patterns connecting the chips, and connection terminals linking these patterns to the second chip, with specific under-bump patterns configured to receive power or ground voltage and efficiently connect to multiple terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips are stacked vertically with traditional connection structures, then the package size is reduced, but the electrical characteristics and structural stability deteriorate
Solution Approach 1:
The connection structure is segmented into multiple functional components: under-bump patterns (separated into first and second patterns), connection terminals, and redistribution layers. This segmentation allows each component to be optimized independently - the under-bump patterns provide mechanical support and electrical connection, while the connection terminals ensure reliable bonding, thereby maintaining reliability in compact stacked packages.
Solution Approach 2:
The patent transitions from traditional two-dimensional planar connections to three-dimensional vertical stacking with multi-layer redistribution. Connection terminals are arranged in multiple layers (first and second redistribution layers) at different heights, enabling efficient vertical interconnection while maintaining electrical performance in the reduced horizontal footprint.
2Volume of moving object
If the package is miniaturized to meet high functionality demands, then the size is reduced, but the power and signal transfer efficiency deteriorates
Solution Approach 1:
Power and signal distribution is extended from two-dimensional planar routing to three-dimensional vertical routing through multiple redistribution layers. The under-bump patterns and connection terminals are positioned at different vertical levels, creating optimized current paths that reduce resistance and improve power transfer efficiency in the miniaturized package volume.
Solution Approach 2:
The under-bump patterns serve as intermediary structures between the connection terminals and the semiconductor chip pads. These patterns provide both mechanical support and electrical conduction, ensuring efficient power and signal transfer through the intermediate connection layer in the compact stacked architecture.
3Ease of manufacture
If traditional under-bump patterns are used connecting to single terminals, then the manufacturing is simpler, but the electrical characteristics and power distribution deteriorate
Solution Approach 1:
The under-bump patterns are designed with multi-functionality: they provide mechanical support, electrical connection, and power distribution simultaneously. Each under-bump pattern is connected to multiple connection terminals (first under-bump pattern connects to two terminals, second under-bump pattern connects to one terminal), enabling the structure to serve multiple functions without significantly increasing manufacturing complexity.
Data Source
AI summary
A semiconductor package may include a lower redistribution layer, a first semiconductor chip on the lower redistribution layer, a second semiconductor chip on the first semiconductor chip, under-bump patterns between the first semiconductor chip and the second semiconductor chip, and connection terminals between the under-bump patterns and the second semiconductor chip. The under-bump patterns may include a first under-bump pattern connected to two of the connection terminals and a second under-bump pattern connected to one of the connection terminals. A power or ground voltage of the second semiconductor chip may be applied through the first under-bump pattern.