Stacked Semiconductor Package Layout for Stable Power Distribution
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving miniaturization, weight reduction, high performance, and reliability, particularly in stacking semiconductor chips effectively to enhance capacity and integration while maintaining high performance and reliability.
Innovation Solution
A semiconductor package design featuring a base substrate with stacked semiconductor chips, where the chips are offset in a staircase structure, and bonding wire structures connect the chips and substrate, with larger pads on certain chips to facilitate efficient electrical connections and improved power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked in multiple stages to achieve miniaturization and high capacity, then the integration density and capacity are improved, but the reliability and power distribution stability deteriorate
Solution Approach 1:
The patent applies local quality by creating different pad sizes at different locations in the chip stack. Specifically, the first pad on the first semiconductor chip has a larger planar area than the pads on lower chips, allowing concentrated power delivery at the top of the stack while maintaining standard connections elsewhere. This resolves the contradiction by providing enhanced power distribution stability (reliability) at critical locations without sacrificing overall integration density.
Solution Approach 2:
The patent introduces a vertical dimension to power distribution by stacking chips with offset arrangements and varying pad sizes at different heights. The first pad extends further in the planar direction compared to pads on lower chips, creating a three-dimensional power distribution architecture. This dimensional approach allows improved power stability at the upper chip level while maintaining high integration density through vertical stacking.
2Area of stationary object
If chip stacking is implemented to reduce package size and weight, then miniaturization is achieved, but manufacturing complexity and precision requirements increase
Solution Approach 1:
The patent employs asymmetry by offsetting semiconductor chips from one another in the stack rather than aligning them symmetrically. The first semiconductor chip is positioned with a different offset than lower chips, and the first pad is designed with a larger planar area extending further in the planar direction. This asymmetric arrangement simplifies manufacturing by providing built-in alignment tolerance, reducing the precision requirements while achieving miniaturization.
3Reliability
If bonding wire structures are used to connect stacked chips, then electrical connectivity is achieved, but power integration issues and signal interference worsen
Solution Approach 1:
The patent uses the first pad with larger planar area as an intermediary element between the first semiconductor chip and lower chips for power distribution. This enlarged pad acts as a mediator that concentrates power delivery and reduces current density in bonding wires, thereby minimizing signal interference and electromagnetic radiation. The intermediary pad structure maintains electrical connectivity while mitigating harmful effects.
Data Source
AI summary
A semiconductor package includes: a base substrate; a semiconductor chip stack including a plurality of semiconductor chips stacked on the base substrate in a first direction and each having an upper surface on which a plurality of pads are disposed; and bonding wire structures electrically connecting the base substrate and the semiconductor chips. The semiconductor chip stack includes a lower semiconductor chip stack and an upper semiconductor chip stack on the lower semiconductor chip stack. The plurality of semiconductor chips include a first semiconductor chip at an uppermost portion of the lower semiconductor chip stack and second semiconductor chips. The plurality of pads include first pads, aligned in a second direction, and second pads, spaced apart from the first pads in a third direction. The first pad on the first semiconductor chip, has an area larger than an area of each of the first pads on the second semiconductor chips.