3D Stacked Semiconductor Package Power Mesh for Low Voltage Drop
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently managing power distribution and reducing voltage drop across multiple stacked semiconductor chips, particularly in three-dimensional stacked structures, which affect performance and efficiency.
Innovation Solution
A semiconductor package design with multiple interconnect layers and power distribution networks for each chip, utilizing distinct power mesh patterns and through electrodes to manage power signals, along with specific pitch distances and overlapping conductive components to optimize power delivery and reduce voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked in a three-dimensional structure, then the functional capacity and integration density are increased, but the voltage drop and power distribution efficiency deteriorate
Solution Approach 1:
The patent transitions from planar power distribution to three-dimensional power distribution by stacking multiple interconnect layers vertically. Power signals are distributed through multiple layers (first interconnect layer, second interconnect layer, third interconnect layer) with through-electrodes penetrating substrates to connect corresponding power regions across stacked chips, enabling efficient vertical power delivery that reduces voltage drop while maintaining high integration density.
Solution Approach 2:
The power distribution network is segmented into multiple independent interconnect layers, each handling specific power signals. The first interconnect layer distributes first power signals, the second interconnect layer distributes second power signals, and the third interconnect layer provides additional power distribution paths. This segmentation allows optimized power delivery for different functional regions and reduces overall voltage drop.
2Loss of energy
If the density of conductive elements is increased to reduce voltage drop, then the power distribution efficiency is improved, but the manufacturing complexity increases
Solution Approach 1:
The interconnect layers serve multiple functions: they provide electrical connection for power distribution, act as mechanical support structures, and enable thermal management pathways. The substrates between chips serve both as electrical isolation layers and as mechanical bonding interfaces. This multi-functionality reduces the need for additional specialized components, simplifying manufacturing despite the three-dimensional structure.
Solution Approach 2:
The patent merges the power distribution function with the interconnect structure itself, rather than using separate dedicated power delivery components. The interconnect layers and through-electrodes simultaneously provide both structural support and electrical connection, reducing the total number of discrete components and simplifying the manufacturing process while maintaining low voltage drop.
3Reliability
If distinct power mesh patterns are used for different power signals, then the power distribution control is improved, but the interconnect layer complexity increases
Solution Approach 1:
Each interconnect layer is designed with specific local characteristics optimized for its function. The first interconnect layer has mesh patterns optimized for first power signals, the second interconnect layer has patterns optimized for second power signals, and the third interconnect layer provides additional localized power distribution. This local optimization allows precise control of power delivery to different functional regions while maintaining manageable complexity through functional specialization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively manages power distribution across stacked semiconductor chips, reducing voltage drop and enhancing overall package performance by optimizing the density and arrangement of conductive elements.
Implementation Method 1
a first interconnect layer including a plurality of first patterns electrically connected to the plurality of first external connection terminals and a plurality of second patterns electrically connected to the plurality of second external connection terminals
Data Source
AI summary
Provided is a semiconductor package including a three-dimensional (3D) stacked structure in which an upper second semiconductor chip is stacked on a lower first semiconductor chip. In the semiconductor package, a power distribution network for the first semiconductor chip and a power distribution network for the second semiconductor chip are implemented through circuits of the first semiconductor chip and separated from the first semiconductor chip.