Stacked Semiconductor Package with Vertical Power Pillar Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in creating smaller, lightweight, and multifunctional semiconductor packages that effectively integrate multiple chips while maintaining high capacity and reliability.
Innovation Solution
A semiconductor package design that incorporates a first semiconductor chip with a signal wiring structure and power wiring structure, a second semiconductor chip with a signal and power wiring structure, and a power connection pillar to connect the two, along with a power wiring substrate, to facilitate efficient power and signal transmission between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If two or more types of semiconductor chips are integrated into one semiconductor package, then the size of the semiconductor package is reduced and capacity is increased, but the complexity of the wiring structure and power distribution increases
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional vertical wiring by introducing via structures that extend through multiple chip layers. Power and signal connections are established in the vertical dimension rather than requiring extensive lateral routing, thereby reducing wiring complexity while maintaining multi-chip integration.
Solution Approach 2:
The power wiring substrate serves multiple functions simultaneously: it provides mechanical support for the stacked chips, establishes electrical connections through integrated via structures, and distributes power to multiple chips through a unified power network. This multi-functional design reduces the number of separate components needed.
2Adaptability or versatility
If multiple semiconductor chips are integrated into one package, then the capacity and functionality are enhanced, but the reliability of power connection between chips becomes more critical
Solution Approach 1:
The patent merges the power connection function with the structural support function by integrating the power wiring substrate as a common foundation for all stacked chips. This unified power distribution network ensures consistent and reliable power delivery to multiple chips through shared via structures and power traces.
Solution Approach 2:
The power wiring substrate and via structures are prepared and positioned in advance before the chips are stacked. This preliminary preparation ensures that power connection paths are pre-established and aligned, reducing the risk of connection failures during the assembly process and enhancing overall reliability.
3Device complexity
If a power connection pillar is disposed within the second semiconductor chip, then the connection is compact, but it may interfere with the second signal wiring structure
Solution Approach 1:
The patent positions the power connection pillar asymmetrically relative to the chip structure, specifically disposing it outwardly of the second semiconductor chip rather than centrally within it. This asymmetric placement allows the power connection to be compact while avoiding interference with the symmetrically arranged signal wiring structures on the chip surface.
Solution Approach 2:
The power wiring substrate acts as an intermediary layer between the first and second chips, providing a dedicated power connection path that does not require the power connection pillar to penetrate through the second chip's active regions. This intermediary structure separates power and signal pathways, eliminating interference.
Data Source
AI summary
A semiconductor package is provided. The semiconductor package comprises a first semiconductor chip including the first signal wiring structure disposed in an upper surface thereof, and a first power wiring structure disposed in a lower surface thereof, a second semiconductor chip disposed on the first signal wiring structure and including a second signal wiring structure, a second power wiring structure disposed on the second semiconductor chip and a first power connection pillar connecting the first power wiring structure and the second power wiring structure to each other.