Stacked Semiconductor Package with RDL-First Testable UBM Structure
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating smaller electronic components into smaller packages while ensuring reliable electrical connections and testing before final assembly, as existing methods lack efficient processes for forming redistribution structures and conducting electrical tests at intermediate stages without compromising component integrity.
Innovation Solution
The 'RDL-first' process involves forming a redistribution structure with tapered recesses and conductive features on a carrier, allowing for pre-assembly electrical testing and subsequent semiconductor device integration, followed by underfilling and molding, which enables identification of defective components and ensures reliable connections through conductive bumps in a ball grid array configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging methods are used, then component integration density is improved, but the ability to perform electrical testing before final assembly is lost
Solution Approach 1:
The patent applies preliminary action by forming the redistribution structure with conductive features and performing electrical tests on the carrier substrate before the semiconductor devices are permanently assembled. This allows defect identification and component replacement while components are still accessible on the carrier, maintaining testing capability despite high integration density.
2Area of stationary object
If smaller packages are used to accommodate smaller components, then area utilization is improved, but the complexity of forming redistribution structures increases
Solution Approach 1:
The patent applies segmentation by dividing the redistribution structure formation into multiple sequential steps: forming dielectric layers, creating recesses, depositing conductive materials, and forming conductive features. This segmented approach manages the complexity of creating intricate redistribution patterns in small packages by breaking down the complex process into manageable, standardized steps that can be performed on the carrier substrate.
3Ease of manufacture
If electrical testing is performed after final assembly, then manufacturing process is simplified, but defect identification and component replacement become difficult
Solution Approach 1:
The patent performs electrical testing as a preliminary action before final device assembly and sealing. The redistribution structure is tested while components remain accessible on the carrier substrate, allowing easy identification and replacement of defective components. After testing, only known-good devices proceed to final assembly, improving ease of repair without significantly complicating the manufacturing process.
Data Source
AI summary
A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.