Stacked Semiconductor Package Recess Structure for Void-Free Bonding
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Solution Overview
Problem
The hybrid bonding method used in multi-chip semiconductor packages is vulnerable to voids generated by contaminants at bonding interfaces, which affects the reliability of the semiconductor package.
Innovation Solution
The semiconductor package design includes a plurality of recesses on the sides of the semiconductor chips, with a deeper recess between the bonding layers to facilitate the expulsion of voids and improve bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If hybrid bonding method is used to directly bond pads to pads, then integration density and miniaturization are improved, but vulnerability to voids from contaminants at bonding interfaces increases
Solution Approach 1:
The bonding interface is segmented into multiple regions by forming recesses at different depths. The first recesses are formed at the semiconductor chip level while the second recess is formed deeper at the bonding layer level, creating staged depth segmentation that facilitates systematic void expulsion during the bonding process.
Solution Approach 2:
The invention introduces a vertical depth dimension to the bonding interface structure by forming recesses at two distinct depth levels. This dimensional approach creates a three-dimensional relief structure that enables voids to be expelled from the bonding interface through the depth gradient, transforming a two-dimensional bonding surface into a multi-level structure.
2Reliability
If recesses are formed to expel voids, then bonding reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The recesses are formed in advance during the chip fabrication process before the bonding operation. The first recesses are etched into the semiconductor chip substrate and the second recess is formed into the bonding layer, preparing the depth-gradient structure beforehand so that void expulsion occurs naturally during bonding without requiring additional complex equipment or processes.
Solution Approach 2:
The invention changes the geometric parameters of the bonding interface by forming recesses with specific depth relationships. The second recess is designed to be deeper than the first recesses, creating a controlled depth gradient that passively guides void expulsion. This parameter-based approach uses simple geometric modifications rather than complex mechanical or chemical systems.
Data Source
AI summary
A semiconductor includes a first semiconductor chip, and a second semiconductor chip provided on the first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate including a first front side and a first back side, and a first back-side bonding layer including a first back-side bonding insulating film, and a first back-side bonding pad, wherein the second semiconductor chip includes a second semiconductor substrate including a second front side that faces the first back side and a second back side, and a second front-side bonding layer including a second front-side bonding insulating film bonded to the first back-side bonding insulating film. A side of the first semiconductor chip includes a plurality of first recesses, which are arranged along a vertical direction, and a second recess, which partially exposes a bottom surface of the second front-side bonding layer between the second front-side bonding layer and the first recesses.