Stacked Semiconductor Package Recess Structure for Molding Reliability
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high-capacity and compact designs while maintaining reliability and yield, particularly in stacked semiconductor chip configurations.
Innovation Solution
The semiconductor package incorporates a first semiconductor chip with a recessed portion in its outer wall and a surface roughness greater than the molding layer, along with a second semiconductor chip stacked on the first chip, and a molding layer that covers the sidewalls of the second chip, enhancing structural integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked to increase capacity, then high-capacity characteristics are achieved, but manufacturing complexity and reliability risks increase
Solution Approach 1:
The chip structure is segmented into functional regions (chip region) and dummy regions with recessed portions, allowing the stacked package to be divided into manageable sections that can be manufactured and assembled separately, reducing overall manufacturing complexity
Solution Approach 2:
Recessed portions are formed in the dummy regions before stacking occurs. This preliminary action prepares the structure in advance to accommodate molding material, preventing manufacturing defects and reducing complexity during the actual stacking and molding processes
2Volume of moving object
If chip size is reduced for compact products, then compact semiconductor packages are achieved, but manufacturing precision requirements increase
Solution Approach 1:
The dummy regions are given different properties than the chip regions, specifically having recessed portions with greater surface roughness. This local quality differentiation allows the compact chip regions to maintain high precision while the dummy regions provide tolerance for manufacturing variations in the molding process
3Strength
If molding layer covers sidewalls of stacked chips, then structural integrity is improved, but surface roughness mismatch may cause defects
Solution Approach 1:
The recessed portions are specifically created in the dummy regions where they will contact the molding layer, while the chip regions maintain their original smooth surfaces. This localized modification ensures proper molding adhesion without affecting the precision of the functional chip areas
Solution Approach 2:
The recessed portions act as cushioning features that accommodate variations in molding material flow and curing. By preparing these features in advance, the design prevents potential defects from surface roughness mismatch between the molding layer and chip surfaces
Data Source
AI summary
A semiconductor package includes a first semiconductor chip having a chip region and a dummy region surrounding the chip region in a plan view, a second semiconductor chip on an upper surface of the chip region of the first semiconductor chip, and a molding layer configured to cover the second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip has a recessed portion in an outer wall of the first semiconductor chip and an upper surface of the dummy region of the first semiconductor chip, and surface roughness of an inner surface of the recessed portion of the first semiconductor chip is greater than surface roughness of an outer wall of the molding layer.