Stacked Semiconductor Package with Redistribution Vias for Reliability
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving miniaturization, weight reduction, high performance, high capacitance, and reliability, particularly in stacking semiconductor chips effectively to enhance electrical characteristics and reliability.
Innovation Solution
A semiconductor package design that includes a substrate with a circuit layer, redistribution structures, connection vias, and vertical connection structures, utilizing different materials for insulating layers and redistribution layers to improve electrical connectivity and reliability, and incorporating an underfill layer and encapsulant for structural support and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of stationary object
If semiconductor chips are stacked in multiple stages to achieve miniaturization and weight reduction, then the package size and weight are reduced, but the electrical characteristics and reliability may deteriorate
Solution Approach 1:
The package is divided into multiple functional layers including substrate, circuit layer, redistribution structures, connection structures, and underfill layers. This segmentation allows each layer to be optimized for its specific function while maintaining overall reliability in the stacked configuration
Solution Approach 2:
The patent employs composite material structures including interlayer insulating layers with different materials, underfill layers, and encapsulants. These composite materials provide both mechanical support and electrical isolation, ensuring reliability while enabling multi-stage stacking
2Area of stationary object
If semiconductor chips are stacked in multiple stages to achieve miniaturization, then the package size is reduced, but the electrical characteristics and reliability may deteriorate
Solution Approach 1:
The patent transitions from planar two-dimensional layout to three-dimensional stacked configuration. Multiple semiconductor chips are arranged vertically in the Z-direction rather than horizontally, achieving miniaturization of the package footprint area while maintaining electrical characteristics through proper vertical interconnection design
Solution Approach 2:
The three-dimensional package is segmented into distinct functional layers (substrate, circuit layer, redistribution structures, connection structures) that are vertically stacked. This segmentation enables efficient use of vertical space while maintaining clear electrical pathways and signal integrity
3Reliability
If multiple redistribution structures and connection structures are added to improve electrical connectivity, then electrical characteristics are improved, but the device complexity increases
Solution Approach 1:
The connection structures serve multiple functions simultaneously: they provide electrical connectivity between stacked chips, mechanical support for the stacked configuration, and thermal management pathways. This multi-functionality reduces the need for separate dedicated structures for each function
Solution Approach 2:
The patent merges the redistribution function and connection function into integrated redistribution structures that combine conductive interconnections with insulating layers. This merging reduces the total number of separate components while maintaining both electrical connectivity and structural integrity
Data Source
AI summary
A semiconductor package includes: a substrate; a circuit layer disposed on a lower surface of the substrate, the circuit layer including an interconnection structure; a first redistribution structure disposed adjacent to the circuit layer, the first redistribution structure including a first redistribution layer; a connection structure including a first connection via electrically connected to the first redistribution layer, a second connection via electrically connected to the interconnection structure, and a connection interconnection interconnecting the first and second connection vias; a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer; a first vertical connection structure disposed on a lower surface of the circuit layer; a second vertical connection structure disposed on a lower surface of the connection structure; and a second redistribution structure disposed below the semiconductor chip and the first and second vertical connection structures.