Stacked Semiconductor Package with Separated Power and Signal Paths
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Solution Overview
Problem
Current semiconductor packages face challenges in miniaturization and integration, leading to signal and power interference and reduced operational reliability due to overlapping signal and power transfer paths.
Innovation Solution
A semiconductor package design featuring a lower redistribution layer with a buried power rail and through electrode connecting to the lower redistribution conductive structure, separating signal and power paths through distinct wiring structures, allowing for efficient signal transmission and stable power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are highly integrated to achieve miniaturization, then device functionality and density are improved, but signal and power interference increases and operational reliability deteriorates
Solution Approach 1:
The patent segments the package into distinct lower and upper portions, with separate power delivery paths for each. The lower power path uses a buried power rail in the lower semiconductor chip, while the upper power path uses a power rail in the upper semiconductor chip. This segmentation isolates power and signal paths, reducing interference and maintaining reliability as integration density increases.
Solution Approach 2:
The patent transitions from planar routing to three-dimensional vertical stacking with separate power rails in different chips. By utilizing the vertical dimension and creating independent power delivery paths through buried rails and through electrodes, the design achieves miniaturization while maintaining signal integrity and reducing interference through spatial separation.
2Device complexity
If signal and power transfer paths overlap to simplify routing, then device complexity is reduced, but signal interference increases and operational reliability deteriorates
Solution Approach 1:
The patent divides the power delivery system into separate segments: a lower power path through the lower semiconductor chip's buried power rail and through electrodes, and an upper power path through the upper semiconductor chip's power rail. This segmentation physically separates power and signal paths, eliminating interference while maintaining routing efficiency through dedicated pathways.
Solution Approach 2:
The patent introduces through electrodes as intermediary structures that connect the buried power rail in the lower chip to the upper redistribution layer. These intermediaries enable independent power delivery without requiring power and signal paths to share common routing channels, thus preventing interference while simplifying overall package design.
Data Source
AI summary
A semiconductor package includes a lower redistribution layer, a lower semiconductor chip and a plurality of conductive connection structures attached to the lower redistribution layer. An upper redistribution layer is disposed on the lower semiconductor chip and the plurality of conductive connection structures. An upper semiconductor chip has an active plane corresponding to an active plane of the lower semiconductor chip and is disposed on the upper redistribution layer. The lower semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first substrate. An upper wiring structure is disposed on the first surface of the semiconductor substrate. A buried power rail fills a portion of a buried rail hole extending from the first surface toward the second surface. A through electrode fills a through hole extending from the second surface toward the first surface.