Stacked Semiconductor Package With Side Via Heat Dissipation
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Solution Overview
Problem
The challenge in semiconductor packaging is to achieve high-performance, multi-functional, and miniaturized electronic devices while reducing the thickness of semiconductor packages, which requires efficient heat dissipation and cost-effective manufacturing processes.
Innovation Solution
A semiconductor package design where the wiring layers of upper and lower semiconductor chips are directly joined, with a mold layer and via formed on one side of the lower chip for heat dissipation and elimination of an internal via formation process, reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wiring layers of upper and lower semiconductor chips are directly joined, then manufacturing cost is reduced by eliminating via formation process, but heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat dissipation by forming the mold layer on the lateral side of the lower semiconductor chip. This lateral positioning creates additional heat dissipation pathways in the vertical and lateral dimensions, allowing heat to escape through the side wall rather than being confined to the top surface, thereby resolving the heat dissipation difficulty while maintaining the direct wiring layer joining structure.
Solution Approach 2:
The mold layer serves as a thermal intermediary structure positioned on the lateral side of the lower chip. This intermediary component provides a dedicated thermal management pathway that interfaces between the heat-generating wiring layers and the external environment, enabling effective heat transfer without interfering with the direct electrical connection between upper and lower chip wiring layers.
2Length of stationary object
If semiconductor package thickness is reduced, then electronic devices become slimmer, but heat dissipation efficiency decreases
Solution Approach 1:
By positioning the mold layer on the lateral side rather than the top surface, the patent creates heat dissipation pathways in the lateral and vertical dimensions. This dimensional approach allows heat to escape through the side wall of the lower chip, providing effective thermal management even when the overall package thickness is reduced for slimmer electronic devices.
Solution Approach 2:
The heat dissipation function is segmented from the traditional top-surface-only approach and distributed to the lateral side through the mold layer. This segmentation creates dedicated thermal management zones that are spatially separated from the stacking structure, enabling effective heat dissipation without increasing package thickness.
3Quantity of substance
If multiple semiconductor chips are integrated into a single package, then capacity and functionality increase, but internal heat accumulation increases
Solution Approach 1:
The lateral positioning of the mold layer on the lower chip's side wall creates heat dissipation pathways that are independent of the vertical stacking arrangement. This allows heat from multiple integrated chips to be efficiently conducted laterally through the mold layer and dissipated to the environment, preventing heat accumulation even as chip integration capacity increases.
Solution Approach 2:
The mold layer acts as a thermal intermediary that collects heat from the lower chip's wiring layers and provides a dedicated pathway for heat evacuation. This intermediary structure is particularly effective in multi-chip packages where heat generation is increased, as it provides a centralized thermal management solution that handles heat from multiple sources without requiring complex cooling systems.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip having a first face and a second face opposite thereto. The first semiconductor chip includes a first wiring layer having a surface that forms the first face. A second semiconductor chip disposed on the first face of the first semiconductor chip includes a second wiring layer directly contacting the first wiring layer. A first mold layer is disposed on one lateral side of the first semiconductor chip and directly contacts the second wiring layer. A first via penetrates the first mold layer. A width of the first wiring layer and the first semiconductor chip in a horizontal direction are substantially the same. A width of the second wiring layer and the second semiconductor chip in the horizontal direction are substantially the same. A height of the first via and the first semiconductor chip in the vertical direction are substantially the same.