Stacked Semiconductor Package Sidewall Insulation for Trace Exposure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face issues with conductive structures at the sidewalls of stacked semiconductor devices, leading to metal migration, corrosion, and shorts, which are not adequately addressed by current methods like etch-back openings or superfluous traces, requiring additional space and increasing the device footprint.
Innovation Solution
Forming cuts in the interposer substrate that intersect bond fingers and fill them with molding material to insulate conductive structures from sidewalls, reducing exposure and preventing migration and corrosion without increasing the device footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods like etch-back openings or superfluous traces are used to address conductive structure exposure, then metal migration and corrosion are reduced, but device footprint increases
Solution Approach 1:
The patent applies dimensionality change by forming stepped structures that create vertical separation between conductive structures and sidewalls. Instead of using lateral extensions (etch-back openings) or additional traces, the invention uses vertical steps to insulate bond fingers and through-substrate conductive structures from the sidewalls, thereby preventing metal migration and corrosion without increasing the device footprint.
Solution Approach 2:
The patent segments the conductive structures by creating separate stepped regions for bond fingers and through-substrate conductive structures. This segmentation allows each conductive element to be independently insulated from the sidewall through its own stepped structure, providing targeted protection against metal migration and corrosion while maintaining compact dimensions.
2Area of moving object
If device footprint is reduced to meet market demands, then circuit density increases, but conductive structure robustness and failure detectability deteriorate
Solution Approach 1:
The patent resolves this contradiction by transitioning from two-dimensional lateral protection methods to three-dimensional vertical stepped structures. This allows the device footprint to be minimized while the stepped structures provide robust insulation and protection for conductive elements, maintaining reliability even in compact configurations.
Solution Approach 2:
The patent applies local quality by creating stepped structures only at specific locations where conductive structures require protection from sidewalls. This localized approach ensures robust protection for bond fingers and through-substrate conductive structures without unnecessarily increasing the overall device footprint, as the stepped structures are formed only where needed.
Data Source
AI summary
Stacked semiconductor packages with features to mitigate trace exposer and associated systems and methods are disclosed herein. In some embodiments, the stacked semiconductor package includes a base substrate, a stack of dies carried by the base substrate, and a mold material deposited at least partially encapsulating the stack of dies. The base substrate can include an active surface and a back surface opposite the active surface. Further, the active surface can include one or more cuts into a peripheral portion of the active surface (e.g., stepped structures at the peripheral edges of the base substrate). The base substrate can also include a plurality of bond pads carried by the active surface over the peripheral portion. Still further, the mold material can fill each of the one or more cuts in the active surface, thereby insulating the bond pads from exposure at a sidewall of the stacked semiconductor package.