Stacked Electronic Package Layout for Shorter Signal Paths
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Solution Overview
Problem
Conventional semiconductor packages face issues with long electrical signal transmission distances and delays, poor electrical performance, and increased volume due to separate integration of memory modules and semiconductor chips, which hinder high-performance and compact design requirements.
Innovation Solution
A stacked electronic package structure with vertically aligned first and second electronic elements embedded in a cladding layer, connected via a circuit structure, and a passive element positioned to reduce signal transmission distances and integrate multiple elements efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory module and semiconductor chip are electrically connected via the circuit structure and routing structure, then the electrical connection is established, but the transmission distance becomes too long, reducing the electrical transmission rate and increasing transmission delay
Solution Approach 1:
The patent transitions from a planar layout where memory module and semiconductor chip are connected through circuit structures to a vertical stacked configuration. The memory module is positioned directly above the semiconductor chip, enabling direct electrical connection through vertical conductive paths (via holes, conductive pillars) that penetrate the cladding layer, thereby dramatically shortening the signal transmission distance and reducing transmission delay.
Solution Approach 2:
The patent embeds multiple electronic components including the semiconductor chip, memory module, and passive elements within a common cladding layer structure. The cladding layer acts as a encapsulating matrix that houses these components in a compact three-dimensional arrangement, with conductive pathways integrated within the cladding layer to establish direct electrical connections between stacked components.
2Adaptability or versatility
If another electronic element is arranged on the routing structure in the cladding layer, then more functions can be integrated, but the layout area needs to be increased, resulting in increase of the overall volume
Solution Approach 1:
The patent utilizes vertical stacking to integrate multiple electronic elements (semiconductor chip, memory module, passive elements) in the vertical dimension rather than spreading them out in the horizontal plane. This three-dimensional arrangement allows high functional integration while maintaining a compact footprint and reducing the overall package volume.
Solution Approach 2:
Multiple electronic elements are nested within the cladding layer structure in a compact three-dimensional configuration. The cladding layer serves as a common encapsulating medium that houses these components efficiently, allowing them to be positioned in vertical stacks or close proximity arrangements that minimize the overall package volume while achieving high functional integration.
3Ease of manufacture
If the semiconductor chip and passive element are integrated in a side-by-side manner, then the layout is simplified, but the signal transmission distance becomes excessively long, resulting in poor electrical performance
Solution Approach 1:
The patent transitions from horizontal side-by-side integration to vertical stacking, where the passive element is positioned above or below the semiconductor chip within the cladding layer. This vertical arrangement creates short direct vertical conductive paths between components, dramatically reducing signal transmission distance and improving electrical performance while maintaining manufacturing feasibility through standardized vertical assembly processes.
Data Source
AI summary
An electronic package is provided, in which a first electronic element and a second electronic element stacked on each other are embedded in a cladding layer, a circuit structure electrically connected to the second electronic element is formed on the cladding layer, and a passive element and a package module are disposed on the circuit structure, so as to shorten the transmission distance of electrical signals between the package module and the second electronic element.