Stacked Semiconductor Package Layout for Balanced Signal Routing
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving compact size, high reliability, superior performance, and increased capacity while ensuring optimized signal routing, simplified wiring, and effective thermal management.
Innovation Solution
A semiconductor package design featuring a flip-chip-mounted lower semiconductor chip and wire-bonded upper semiconductor chip stack, with aligned command and address signal pads and distributed data signal terminals, ensuring equal connection distances and reduced wiring complexity, and improved heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-dimensional grid pattern is used for connection terminals on the PCB, then the package structure is simple and easy to manufacture, but the package size increases and capacity is limited
Solution Approach 1:
The patent transitions from a two-dimensional grid arrangement of connection terminals to a three-dimensional chip stack architecture. Multiple semiconductor chips are stacked vertically with inter-chip connections, enabling capacity expansion in the vertical dimension rather than expanding the horizontal PCB area. This dimensional change allows higher capacity while maintaining compact package size.
2Quantity of substance
If multiple semiconductor chips are integrated to increase capacity, then the package capacity increases, but the wiring complexity and number of layers increase
Solution Approach 1:
The patent divides the semiconductor package into multiple independent chip stacks, where each stack contains one or more semiconductor chips connected through the package substrate. This segmentation allows each stack to be relatively simple in structure while the overall package achieves high capacity through the combination of multiple stacks. The package substrate provides a common platform that simplifies inter-chip connections compared to direct chip-to-chip wiring.
3Reliability
If chip stacks are arranged to optimize signal routing, then signal integrity improves, but the package area increases
Solution Approach 1:
The patent combines multiple chip stacks within a single package substrate, sharing common connection terminals and signal routing resources. By merging the substrate infrastructure among multiple stacks, the package area is efficiently utilized while maintaining signal integrity through controlled impedance paths and proper terminal assignment for each channel.
Data Source
AI summary
A semiconductor package includes a package substrate having connection terminals. The connection terminals include first to fourth DQ terminals, and first and second CA terminals. A first chip stack has a first semiconductor chip flip-chip-mounted and connected to the first DQ terminals, and a fourth semiconductor chip on the first semiconductor chip wire-bonded to be connected to the fourth DQ terminals. A second chip stack has a second semiconductor chip flip-chip-mounted and connected to the second DQ terminals, and a third semiconductor chip on the second semiconductor chip wire-bonded and connected to the third DQ terminals. The first and third semiconductor chips are commonly connected to the first CA terminals, and the second and the fourth semiconductor chips are commonly connected to the second CA terminals.