Stacked Semiconductor Package Layout for Smaller Footprint
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving a small size, high density, low power consumption, multifunctionality, high signal-processing speed, high reliability, low cost, and clear image quality, particularly in image sensor chips.
Innovation Solution
A semiconductor package design featuring a first semiconductor chip with a glass pattern on one surface, a second semiconductor chip electrically connected to the first, and a molding pattern bordering the side surfaces, along with a re-distribution structure on the second chip's surface, allowing for reduced area and increased connection flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional semiconductor package design is used, then the package structure is simple and easy to manufacture, but the package area is large and connection flexibility is limited
Solution Approach 1:
The patent transitions from a conventional planar package layout to a three-dimensional stacked architecture. Multiple semiconductor chips are vertically stacked and interconnected through through-vias, enabling spatial utilization in the vertical dimension. This dimensional change reduces the horizontal package footprint while accommodating complex interconnections through the vertical stacking approach.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked one on top of another, with lower-level chips supporting upper-level chips. The through-vias penetrate through multiple chip layers, creating a nested interconnection pattern where connection paths are embedded within the stacked chip structure, achieving compact integration similar to nested dolls.
2Area of moving object
If the package area is reduced, then high density and small size are achieved, but manufacturing precision and alignment requirements increase
Solution Approach 1:
The patent employs preliminary alignment features such as alignment marks and positioning structures formed on the semiconductor chips before stacking. These pre-formed alignment references enable precise registration of through-vias across multiple chip layers during the stacking process, ensuring accurate interconnections without requiring extremely tight manufacturing tolerances.
Solution Approach 2:
The patent introduces intermediary alignment structures and positioning layers that facilitate precise alignment between stacked chips. These intermediary elements act as mediators that transfer and maintain alignment accuracy across multiple stacking operations, reducing the cumulative alignment error that would otherwise occur in direct multi-chip stacking.
3Adaptability or versatility
If multiple semiconductor chips are stacked to reduce area, then connection flexibility increases, but the number of interconnection structures increases
Solution Approach 1:
The patent designs the through-via interconnection structures to serve multiple functions simultaneously. The same via structure provides both mechanical support for stacking and electrical interconnection between chips. Additionally, the standardized via design can accommodate different signal types (power, ground, data) through variations in via filling and routing, reducing the need for separate specialized interconnection structures.
Solution Approach 2:
The patent divides the interconnection function into discrete through-via segments that can be independently formed and configured in each chip layer. This segmentation allows flexible routing patterns and connection topologies to be achieved by selectively forming and connecting via segments across different layers, managing complexity through modular interconnection units.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip having a first surface and a second surface opposite to each other, a second semiconductor chip on the second surface of the first semiconductor chip and electrically connected to the first semiconductor chip, and a molding pattern bordering side surfaces of the first semiconductor chip and side surfaces of the second semiconductor chip. At least a portion of the first surface of the first semiconductor chip is free of the molding pattern. A glass pattern is on the first surface of the first semiconductor chip.