Stacked Semiconductor Package Structure for Precise SoIC Bonding
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging System-on-Integrated-Chip (SoIC) components due to issues related to packaging processes, which hinder miniaturization, higher speed, greater bandwidth, and lower power consumption.
Innovation Solution
A method involving chip-to-wafer fusion bonding, followed by hybrid bonding and encapsulation processes, is used to create a stacked structure of semiconductor dies with precise alignment and conductive connections, utilizing silicon and silicon dioxide bonding layers and dielectric materials, along with warpage control through support substrates and backside metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chip-to-wafer fusion bonding is used to achieve precise alignment, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The packaging process is divided into distinct stages: first bonding semiconductor dies to a carrier wafer, then bonding the carrier wafer to a support substrate, and finally removing the carrier. This segmentation allows each bonding step to be optimized independently for precision while managing overall process complexity.
Solution Approach 2:
A carrier wafer is introduced as an intermediary substrate to facilitate the bonding process. The carrier wafer enables precise alignment and bonding of multiple semiconductor dies, then serves as a temporary support during subsequent processing steps before being removed after transfer to the final support substrate.
2Productivity
If multiple semiconductor dies are stacked to increase integration density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking of semiconductor dies. Multiple dies are bonded vertically on top of each other on the support substrate, utilizing the vertical dimension to increase integration density while maintaining precise alignment through the carrier wafer bonding process.
Solution Approach 2:
Semiconductor dies are pre-bonded to the carrier wafer in a controlled manner before being transferred to the support substrate. This preliminary arrangement ensures precise positioning and alignment is achieved during the first bonding step, which then facilitates accurate stacking when transferred to the final substrate.
3Length of stationary object
If thin semiconductor structures are used to reduce thickness, then length is improved, but structural integrity deteriorates
Solution Approach 1:
The patent employs a composite structure consisting of multiple thin layers including semiconductor dies, carrier wafer, support substrate, and encapsulation material. Each layer contributes specific properties, and their combination provides both reduced overall thickness and sufficient structural integrity through the distributed strength of multiple bonded interfaces.
Solution Approach 2:
Thin semiconductor die layers and encapsulation films are used to minimize package thickness. These thin structures are made structurally sound through precise bonding to underlying substrates and the use of support substrates that provide mechanical strength while allowing the overall package to remain thin.
4Reliability
If hybrid bonding processes are used to achieve conductive connections, then electrical conductivity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple bonding approaches into a hybrid process: chip-to-wafer fusion bonding for the initial die-to-carrier attachment, followed by wafer-to-wafer bonding for carrier-to-support-substrate attachment. This merging of bonding techniques achieves reliable electrical and mechanical connections while managing process complexity through systematic integration of different bonding methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and reliability of SoIC components, improving yield and reducing thickness variations while maintaining structural integrity and electrical connectivity.
Implementation Method 1
chip-to-wafer fusion bonding
Data Source
AI summary
A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.