Stacked Semiconductor Package Warpage Prevention
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices leads to larger chip and package sizes, causing warpage issues during mounting on printed circuit boards, which can result in short circuits and delamination, especially when using stacked package technologies like system in package (SIP) and package on package (POP) approaches.
Innovation Solution
A method of fabricating a stacked package using semiconductor packages with specific solder materials and melting temperatures, where first solders with a high melting temperature and solder paste nodes with a lower melting temperature are annealed to form inter-package bonding units, and additional solders with varying melting temperatures are used for mounting on a package board, minimizing thermal load and preventing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor packages are stacked to form a smaller overall package, then the package size is reduced, but warpage occurs during mounting causing short circuits and delamination
Solution Approach 1:
The patent applies parameter changes by using multiple solder materials with different melting temperatures (first solder with higher melting temperature, second solder with lower melting temperature). This allows staged bonding during annealing, where the first solder bonds the upper package to the lower package at higher temperature, and the second solder bonds the lower package to the PCB at lower temperature. This temperature parameter differentiation enables the stacked package to be mounted without excessive thermal stress that would cause warpage, while achieving reliable inter-package and board-level connections.
Solution Approach 2:
The patent uses composite materials by combining different solder materials (first solder and second solder with different melting characteristics) in the bonding structure. The first solder material (e.g., Sn-Ag-Cu alloy with higher melting point) and second solder material (e.g., Sn-Pb alloy with lower melting point) work together in a composite bonding system. This composite approach allows the structure to withstand the mechanical and thermal stresses of stacking while enabling reliable mounting without warpage-induced failures.
2Reliability
If discrete packaging and electrical testing are performed on each semiconductor package before stacking, then package functionality is ensured, but fabrication complexity and time increase
Solution Approach 1:
The patent applies preliminary action by performing electrical testing and functional verification on each semiconductor package before the stacking process. The upper and lower packages are individually packaged, tested, and confirmed functional prior to being bonded together. This preliminary validation ensures that only functional packages proceed to stacking, preventing assembly of defective units. While this adds fabrication steps, it eliminates the need for complex post-assembly testing and rework, ultimately simplifying the overall fabrication process.
3Strength
If high melting temperature solder is used for inter-package bonding, then bonding strength is improved, but thermal stress increases causing warpage
Solution Approach 1:
The patent resolves this contradiction by changing the temperature parameter through staged annealing. The first solder (higher melting temperature) is bonded at a higher temperature (e.g., 200-300°C) to achieve strong inter-package bonding. Then, the second solder (lower melting temperature) is bonded at a lower temperature (e.g., 150-250°C) to attach the package to the PCB. This parameter differentiation allows strong bonding where needed while minimizing thermal stress during the second bonding operation, preventing warpage while maintaining bonding strength.
Solution Approach 2:
The patent applies segmentation by dividing the bonding process into two separate stages with different temperature parameters. The first bonding stage uses high-melting-temperature solder for inter-package bonding, and the second bonding stage uses low-melting-temperature solder for board mounting. This segmentation of the bonding process allows each stage to be optimized independently - the first stage achieves maximum bonding strength, while the second stage minimizes thermal stress and warpage risk.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermal stress on the packages, prevents defects like electrical shorts and delamination, and ensures stable mounting of stacked packages by utilizing transformed solder paste nodes with higher melting temperatures and strategically placed solders, thereby facilitating the miniaturization and integration of semiconductor packages.
Implementation Method 1
forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature
Implementation Method 2
the solder paste nodes are transformed into a material having a third melting temperature higher than the second melting temperature
Implementation Method 3
mounting the stacked semiconductor package on a package mounting board by attaching the package mounting board to the second solders by performing annealing at a temperature higher than the fourth melting temperature and lower than the first and third melting temperatures
Data Source
AI summary
Provided are a stacked package, method of fabricating a stacked package, and method of mounting a stacked package. A method includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.